Enhance Your Design and Verification Knowledge with Extensive Webinar Series

There is no easier way to learn new material than with a webinar in the comfort of your own home or office. Webinars bring experts directly to you with the latest results from both research and practical experience. Live webinars offer immediacy and interaction, while recorded webinars offer the chance for many more participants to benefit from the material over time. At Agnisys, we have found that webinars are an excellent way to educate the industry on key design and verification challenges in IP/FPGA/ASIC development. With the current circumstances in the world and so many engineers working from home, all forms of online learning are more important than ever.

With this perspective, we are pleased to announce an extensive series of webinars over the next three months that will cover a broad range of design and verification topics. Please note that these are not just recorded sales presentations. Our technical experts have gone to considerable effort to provide background on industry challenges, consider possible solutions, and outline the approaches that have worked best for our users. We are presenting solid technical content backed by real user experience with our solutions on successful IP/FPGA/ASIC projects. Here is our current schedule of upcoming webinars:

• Creating portable UVM sequences with ISequenceSpec
  • Date: 9-April-2020, Time: 10:00 AM-11:00 AM PDT

• Register automation from SystemRDL to PSS – Basic to Pro
  • Date: 16-April-2020, Time: 10:00 AM-11:00 AM PDT

• Cross platform specification to code generation for IP/SoC with IDS-NG
  • Date: 23-April-2020, Time: 10:00 AM-11:00 AM PDT

• Advanced UVM RAL – callbacks, auto-mirroring, coverage model, and more
  • Date: 30-April-2020, Time: 10:00 AM-11:00 AM PDT

• Functional safety and security in embedded systems
  • Date: 7-May-2020, Time: 10:00 AM-11:00 AM PDT

• IP generators – the next wave of design creation
  • Date: 14-May-2020, Time: 10:00 AM-11:00 AM PDT

• A flexible and customizable flow for IP connectivity and SoC design assembly
  • Date: 21-May-2020, Time: 10:00 AM-11:00 AM PDT

• Steps to setup RISC-V based SOC Verification Environment
  • Date: 28-May-2020, Time: 10:00 AM-11:00 AM PDT

• Automatic verification using Specta-AV – a boost to verification productivity
  • Date: 04-June-2020, Time: 10:00 AM-11:00 AM PDT

• AI based sequence detection for verification and validation of IP/SoCs
  • Date: 11-June-2020, Time: 10:00 AM-11:00 AM PDT

• Understanding clock domain crossings
  • Date: 18-June-2020, Time: 10:00 AM-11:00 AM PDT

As you can see, the topics across this webinar series are quite diverse. They encompass many disciplines, from design and verification to portable stimulus, system architecture, safety, security, and artificial intelligence. We are certain that you will find many of these webinars of interest and a wise investment of your valuable time. You can register here at your convenience. We look forward to seeing you online!

Tags: Agnisys, Design, Design Assembly, webinar, Webinar series

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