A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the key building blocks for the simulation testbenches at the heart of the DV process. The previous post focused on correct-by-construction of UVM testbenches using the DVinsight™ smart editor from Agnisys. This post shows how other solutions from Agnisys can automate the generation of the UVM Register Abstraction Layer (RAL) that provides testbench access to the registers and memories in the design being verified.
Archive for May, 2020
Most of us have faced difficulties in our personal and professional lives, and have worked our way through them. But few of us have experience dealing with a challenge as broad and disruptive as the COVID-19 global pandemic. By now, many people know friends and family members who have been sickened or even struck down by this disease. The economic toll is staggering, and recovery will take considerable time. Even with all the coping mechanisms we have developed through dealing with past challenges in our lives, it’s easy to feel overwhelmed.
I think that the best way to handle the stress and uncertainty is to do whatever we can to help our families and community, and those everywhere suffering directly or indirectly from the virus. As an example, a diverse group of companies and institutions recently took an innovative step to establish the Open COVID Pledge. This initiative offers intellectual property (IP) free of charge for the purpose of diagnosing, preventing, containing, and treating COVID-19.