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 Agnisys Automation Review

Archive for April, 2020

Correct-By-Construction SystemVerilog UVM Testbenches

Thursday, April 23rd, 2020

Modern RTL design verification (DV) environments are both very powerful and very complex. They include advanced simulation testbenches plus support for formal verification, virtual prototypes, and emulation technology. Even within just the testbench, there is a great deal of highly sophisticated code to be written. Part of the power and complexity comes from the capabilities of the testbench. At the core is constrained-random stimulus generation, automated tests that exercise many parts of the design while staying within the rules for input sequences. Important testbench components include interfaces, register models, bus agents, reused verification IP (VIP), results checkers, and coverage monitors. Clearly, a lot of effort is needed to create and maintain this infrastructure. A typical infrastructure is shown in the following diagram:

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Enhance Your Design and Verification Knowledge with Extensive Webinar Series

Wednesday, April 8th, 2020

There is no easier way to learn new material than with a webinar in the comfort of your own home or office. Webinars bring experts directly to you with the latest results from both research and practical experience. Live webinars offer immediacy and interaction, while recorded webinars offer the chance for many more participants to benefit from the material over time. At Agnisys, we have found that webinars are an excellent way to educate the industry on key design and verification challenges in IP/FPGA/ASIC development. With the current circumstances in the world and so many engineers working from home, all forms of online learning are more important than ever.

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