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Archive for June, 2020

Smart Assembly of SoC Designs

Monday, June 29th, 2020

System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design, and verification are all challenging. This blog post focuses on the challenges faced by designers, driven by the convergence of applications onto a single SoC device. This increases the demand for design functionality and design performance. At the same time, market requirements generate pressure to drive down the cost of design and meet shrinking market windows due to shorter product shelf lives. Every step of the design process has become more difficult, even the seemingly simple task of assembling all the pieces that make up the SoC.

Today’s large chips may contain 500 of more instances of intellectual property (IP), a combination of new designs, reused blocks from previous projects, and licensed commercial IP. If each of these blocks averages 50 ports, then 25,000 connections must be made among them. Making these connections manually is tedious and time-consuming, with a high chance of errors. Meeting cost and schedule goals requires a big increase in the productivity of the SoC design team. Methodology improvements are needed to help accelerate assembly of chips and systems through automation.


The best solution is providing designers flexible, customizable, and configurable IP and subsystem generators along with a tool to automate architectural level SoC assembly and connectivity. The capabilities for such a solution include:

  • Creating and editing the design on the fly through scripts or a command line interface
  • Generating major subsystems with flexibility to customize or configure
  • Automatically adding instances to the design, making connections, restructuring, etc.
  • Viewing the resulting schematics for design analysis
  • Running design rule checks to endure IP and SoC quality
  • Generating appropriate files for design, verification, and software teams


Three Steps to Set Up a RISC-V SoC UVM Testbench

Wednesday, June 17th, 2020

Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one or more embedded processors, and the code they execute provides a significant portion of the overall functionality. Both the hardware and software must be verified, but they also must be verified together (co-verified) to exercise the full range of intended operation. Although lint checks, formal analysis, and other techniques play a role, the bulk of verification is performed by simulating a testbench compliant with the Universal Verification Methodology (UVM) standard.

Such a testbench environment is a must-have requirement for every SoC project. It provides a means to check the full system before sending the design to the foundry for fabrication. It complements block-level testbenches by verifying that all the connections between the blocks are functioning correctly, that data flows properly around the SoC, and that hardware interrupts and their associated interrupt service routine (ISR) software are working. The testbench can also help the firmware and software engineers write and debug device drivers and applications. Setting up the SoC verification environment can be divided into three steps:

  • Creating a testbench compliant with the UVM architecture
  • Converting C programs to binary files for the embedded processor(s)
  • Synchronizing C programs and UVM tests

The process is similar for any type of embedded processor, but this post focuses on RISC-V since it is a widely used instruction set architecture (ISA) for contemporary SoCs.


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