Automating Design Assembly

The consumer revolution over the past few decades has funneled a growth of SoC chips primarily in the area of consumer electronics. This revolution along with the increase of automotive and industrial electronics has led to a trend in convergence of applications on a single device. Companies vying for a bigger share of the market place are enticing their consumers by offering new or better features, which often adds to design complexities. In this competitive food chain, chip design companies are tragetting the companies developing these consumer devices with a range of functionalities embedded in single chip solutions. This convergence in applications as well as the growth of new technologies such as IoT, augmented reality, AI etc. has resulted in increasing demands on design complexity and design performance.  With an increase in design complexity and a reduction in time to market, chip designers are now grappling with ways to meet the performance requirements while at the same time reduce the design cycle.

Consequently, design teams are increasingly compelled to look at methodology changes that can help accelerate chip assembly through one or multiple forms of automation.

Using internal scripts & spreadsheets for design assembly

A complex SoC usually contains a large number of IPs and IP sub-systems, many of which may have more than 100’s of ports. Creating the thousands of connections in HDL through a text editor, and reviewing the same, is an extremely arduous task. With an objective of solving this vexing problem and optimizing the design assembly process, designers are looking for ways to automate the process of making the desired design connections as well as reduce the number of errors made in design connectivity. To improve design productivity, many have migrated to an approach of creating reusable IP’s, which describes the functionality and then can be structurally connected with other IP’s. And rather than connect the IP’s using text editors, designers have started using internal scripts or spreadsheets or a combination of both to make the connections. The connectivity information for assembling a design in typically captured in a spreadsheet (Excel), and then a script is written to convert the spreadsheet to a RTL netlist. An advantage of using scripts to make the design connections and RTL generation is that syntax and design connectivity errors are reduced to some extent.

This approach is widespread in major semiconductor companies, with few top-level or block level netlists are created manually. But, as in all technology advances, the first implementation quickly shows limitations. The solution is typically the brainchild of a dedicated designer with a flair for scripting. While these work well for that designer, they rarely transfer successfully to other design teams. Other teams want changes, backward compatibility and on-going support – something the original inventor never intended to provide. Design modifications, debug and analysis of the designs created is another area, which tends to be rather problematic. While the scripts may create the desired connectivity, validating the sanctity of the design rules is a rather complex task and very often beyond the scope of scripts. Modifying existing designs easily to create derivatives is yet another facet, which adds complexity to the scripts being created.

To solve this problem, the IEEE 1685 standard originally launched in 2003 by a consortium of industry leaders such as NXP, ST, ARM along with a number of EDA companies aimed at introducing standards for design assembly. Rather than tying data definition to proprietary spreadsheet tools, the consortium defined the IP-XACT standard based on XML, an open data standard. To reduce the complexity of connecting the blocks, bus definitions similar to the concept of interfaces in System Verilog™ were also added.

Abstracting the port and connectivity

Using the IP-XACT standard was the first step in automating the design assembly process. Productivity can be enhanced considerably if the number of connections to be made can be reduced drastically. Abstraction of the ports or nets could be for a standard protocol such as AXI, AHB, PCI or proprietary buses etc. An interface, which typically contains a collection of logical ports and logical port characteristics helps reduce the total number of connections required in a design. It also minimizes the scope of making errors during connection.

But all IP’s unfortunately do not have the IP-XACT definition associated with it. Designers still rely on the top level RTL for the IP to make the desired connections. Mixed RTL designs are in vogue these days with designers using a mix of Verilog, VHDL & System Verilog designs. IP’s can be in any language and designers are willing to use them for their designs as long as it meets their criteria. In order to leverage existing RTL or third party IP while creating designs, a designer is now burdened with the task of having to know the semantics of all the languages.

To get around this problem, big companies have resorted to standards such as IP-XACT (now IEEE 1685) to package the IP’s and then connect them using a combination of generators. However designers who have not migrated to the standards still have the need to be able to read in existing designs and make modifications to create derivatives or quickly create new designs leveraging of existing RTL. They are now compelled to ensure that their solution is able to read in RTL, and able to map the ports to interfaces to facilitate design assembly as well as generate syntactically clean RTL.

Key features of a design assembly solution

When considering solutions, it is important to check carefully what aspects of the design process are covered by the tool. A reasonable checklist should at least include:

• Ability to import/export RTL
• Ability to define user defined properties, which can be used by generators.
• Compliance with existing standards such as IP-XACT (now IEEE 1685-2014).
• Flexibility to abstract ports to efficiently capture connections.
• Ability to easily reconfigure an IP as needed or update the current version with a later version.
• Support for concurrent design development.
• Support for interface to internal tools and other third party tools.
• Ability to easily specify tie-offs, intentional opens and other special cases, where needed.
• Built in Design Rule Checks to validate design connectivity before generating RTL. Flexibility to add custom DRC checks should also be available.
• Support for generating documentation.

THE AGNISYS SOLUTION

Agnisys has leveraged its mature register solution along with its new standard library of customizable & configurable IP generators (SLIP-G) to offer an integrated solution called SoC Enterprise, which provides a flexible and customizable environment for design assembly to meet specific design requirements. In addition to supporting the key features of an assembly solution, SoC Enterprise is a very fast assembler for enterprise level SoC development teams spread around the world. In fact, it’s more than an assembler, as it can also generate components like aggregator, bridges, channels, bus fabrics and muxes.

SoC Enterprise supports command mode through text-based APIs and GUI mode. It can include IPs created from following sources: …

• IP created by the user manually
• IPs generated by SLIP-G,
• RTL/IP-XACT generated from specifications using IDesignSpec,
• Third party IPs in RTL/IP-XACT format.

SoC Enterprise saves the user a large amount of time by its automation. Quite soon it will become a must have for every SoC design and verification team.

Tags: Agnisys, Design Assembly

This entry was posted on Tuesday, March 3rd, 2020 at 9:48 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.