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Introduction
Gold Gate Technology is a small venture backed startup offering power reduction products and services for IC designers. Last May they introduced two new software products -- Power Optimize Gold and Power Plan Gold. On August 11th they announced the appointment of William Ruby as VP of Marketing. I had an opportunity to interview him shortly thereafter.
Tell me a little about your background.
I started out as an IC designer. Actually one of the very first jobs I had at Intel was as part of the first Pentium design team. I designed the Pentium cache memory. I spent quite a few years at Intel. I then took a medical position at Siemens which was doing pacemakers. I was interested in low power even back then. I thought it would be an opportunity to learn about low power design. I worked at Siemens for about four years. I also went to business school at the same time. I thought that EDA would be an interesting place to work since I had used design automation tools as a designer. I thought that working in the field seem the thing to do. When I was at Siemens I used the EPIC tool called Power Mill, one of the first power analysis tools. Quite a few people at EPIC were aware of that, gave me a call and brought me on board. I was responsible on the marketing side for their power analysis and power characterization products. A few months after I joined EPIC it became part of Synopsys. I was at Synopsys for four years. I left and took a detour to a little startup that I was attracted to. Eventually I wound up at a place called Sequence Design. Sequence in my opinion was not really focused on a particular strategy. They tired to do a lot of different things. They are still around but nobody is really sure there they are going. I wanted to get back to a larger place, basically a safer place to be than Sequence. I went to Cadence for a year and a half. I didn't have much to do with power at Cadence. I was running Cadence Virtuoso physical design product.
Golden Gate was a company that Sequence was trying to do a partnership with and I was engaged in that effort. They originally started out doing a full blown place and route technology and later the company focused on power reduction specifically and that's where my background fits very well. I was brought on board. I'm responsible for Marketing and actually application engineering as well; custom support pre-sales and post sales.
What attracted you to Golden Gate?
Two things. Number one is the real laser sharp focus of the company, specifically in the area of power reduction. There are a lot of capabilities out there that perform power analysis and power information. They tell you how much power your design is using but they don't do very much about fixing the problem. Golden Gate is specifically addressing the issue of reducing power consumption automatically and working together with existing design flows. To me that's a very good value proposition, a defensible market position. I think that with this kind of approach Golden Gate will be successful. It's a small company atmosphere. It is more of an entrepreneurial spirit and team. On the front line being able to make a direct contribution to the company's success.
The focus on power reduction as well as the small company atmosphere, that's what attracted me.
In your role as head of Marketing what is the main challenge?
I think one of the biggest challenges of marketing for a small company is rising above the noise level. There are a lot of small companies out there and obviously the larger vendors. But from a marketing perspective, honing the message and coming up with the positioning of the product with unique technology to really provide value to the customers out there; focusing on that value; showcasing that value; and really just differentiating the company and its technology from everyone else. This is the real challenge on the marketing side. I'm spending a lot of time right now on the product roadmap and product specification, benchmark results trying to get a handle on the unique technology that Golden Gate has and getting the value which is power reduction quantified and show to the customer.
Why is power reduction so important?
There are at least three reasons why power reduction is important. One good reason is that that everything is going wireless, everything is going portable these days, everything runs on batteries. The longer the battery lasts, the more competitive the product is, the better consumers like it and the more visible a particular end product is from our end customer. Cellphones, PDAs, wireless game systems like the Sony PSP, anything that runs on batteries. For them power reduction is absolutely critical because of the longer battery life requirement. There is never enough talk time on cellphones, never enough play time on a gaming system. Battery life is absolutely critical.
The second reason is cost. It turns out that the price of a package even the type of package that a semiconductor chip is put on and therefore the cost of the package is a direct function of its power consumption. The more power a chip consumes the more expensive is the package required to dissipate that heat. In some cases you need a heat sink or a fan to dissipate the extra heat. If a design team can reduce the power consumption of a design they can potentially reduce the packaging costs and therefore improve the profit margin. Power is becoming a limiting factor in some cases, limiting the sheer functionality of the design. I've heard Intel say in public that in the past they did high performance design but nowadays they do power constrained high performance design. This means in the past it was all about clock speed and how fast you could go while nowadays it is how fast you can go under a particular power budget. This is a very interesting area where power reduction can potentially lead to higher functionality and higher clock speed.
The third reason is sheer reliability. We talked about packaging costs. What happens is that you consume too much power for the package you have designed the chip for. I've seen a processor chip putting out the system and begin to smoke at the same time. Short term and long term reliability is a direct function of heat and therefore power consumption. Reducing power will improve the reliability of the device. A typical failure of a part in a system, particularly one in the hands of the customer in the field, can be enormously expensive to correct. It's better to catch these problems early. Make sure the design is done properly and avoid the chip blowing up.
Pat Gelsinger now Intel CTO said in an article “Chipmakers Face Power Struggles” in the San Francisco Chronicle said that “Business as usual is not an option” What he meant is that you can't ignore power consumption in your design, you have to actively find ways of reducing it in your design flow. You must deal with it every step of the way.
What do you see as the mission of Golden Gate?
Our mission is to be the gold standard for power reduction. It really means we want to build up the franchise of the company by looking at all aspects and all elements of power consumption focused on reducing all of these components and all these elements of power including dynamic and switching power, heat power and leakage power. Looking at how power is distributed on the chip. Looking at ways to optimize and reduce power consumption.
Tell me a little bit about the company.
The company was founded about four years ago. The initial focus was on place and route technology that still forms the base for power consumption. We have a team of about 50 people in Moscow. We have several active customers in the semiconductor community doing tape outs with our technology. We are a small ventured funded company. We are funded in part by Horizon Ventures, a small VC firm, and by Lightspeed Venture Partners, a bigger firm that has provided most of the investment ($9 million in May 2004). We are protective of our technology. We have filed half a dozen patents and are in the process of filing several more.
How many people in total?
We have 65 people. About 15 in the US and 50 I Ruswia. In the US we have the executive team, sales and application engineering. We also have a couple of key developers in the US.
What is the Golden Gate's revenue?
We a private company and can't comment on revenue at this time. The install base is several customers. On our website ( www.ggtcorp.com) you can see three EASIC, Lightspeed (no relation to the VC firm) and Oki Semiconductor. I can tell you that we are now in active evaluation with at least half a dozen customers looking at our power reduction tools.
What is Golden Gate delivering?
We deliver automatic power reduction of 15-20% on top of established or existing design flows such as Cadence, Synopsys and Magma. We work with the existing flows and infrastructures. We don't replace the major capabilities in the established design flow. We have very fast turn around time, typically overnight for a 500K gate block. We guarantee that we maintain timing, signal integrity and em concerns and come out with DRC clean designs.
Is there any limit of the number of gate blocks?
We support both 32 bit and 64 bit operating systems. In the 32 bit case you are kind of limited by available memory. We will route roughly about a million instances depending upon the design. Typically the number of placed instances is a hard measure while equivalent gates is more like a multiple of the gates you use. In terms of instances three quarters of a million for a 32 bit machines. For 64 bit machines we haven't seen a limit. It's just a matter of how much memory you load up on your machine. For all practical purpose on a 64 bit machine we have no limit.
What products do you offer?
We have two basic products. Power Optimizer Gold and Power Plan Gold. Power Optimizer Gold offers power reduction and power optimization. Power Plan Gold trys to create a power deliver system, power grid, power mesh on the chip.
Power Optimize Gold automatically reduces power by typically 15-20% within existing flows addressing both switching and standing leakage power consumption. We employ a unique technology that we call WiresFirst. The results meet timing, SI and EM considerations.
We have three power reduction techniques at this point. We have clock power optimization which is the actual starting point early in the implementation flow. Then we have the WiresFirst optimization that is performed on routed designs and lastly we have incremental optimization. Today we are developing a few more and will be rolling these out at the end of this year and next year to address different component of power.
We fit into the traditional flow (see diagram below). Remember we are in the physical implementation space, the place and route space. The first place we come in is we can start reducing power at the placement phase. After the physical synthesis is done, we have the initial placement. We can modify the placement, we can optimize cells to reduce power consumption by essentially doing the placement changes that would result in the clock tree synthesis tool routing shorter wirelengths. This is placement based optimization. Once we have that optimized placement that goes back into the design flow where clock tree synthesis, routing and detailed routing is being performed. Again we are not solving the timing closure problem, we are working with existing timing of the design in reducing power consumption. Once the optimized placement goes back in the user do clock tree place and route, whatever they have to do to solve timing. We can take that design and now start with WiresFirst. First of all it will understand because the design is routed at that time that the timing is already set. That presents to us a hard constraint on timing. The algorithm we use maximum total delay maintains timing. WiresFirst does a complete routing optimization to reduce the power consumption of the design. WiresFirst also performs incremental optimization which is more like surgically fixing one cell at a time. It introduces small perturbations, small placement change, small routing changes that provide some power saving but it doesn't re-optimize the entire routing of the design. WiresFirst includes incremental optimization but it can be used separately if that what a user desires. Once WiresFirst is done with routing optimization we output a fully routed and placed design which meats timing and is DRC clean. This goes back into the flow for verification and any additional work that is required.
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Expand a little on WiresFirst.
What we have recognized working with physical design area is that wires or interconnects on the chip are now really beginning to dominate power consumption just as a few process nodes ago the interconnect began to dominate timing. What WiresFirst does is that it will reduce power consumption by minimizing capacitance of those routes that have high switching activity. It understands the affinity of the circuit from either simulation inputs or activity estimating algorithms and then tries to minimize that capacitance. Power is obviously proportional to capacitance and activity. So you see how power consumption goes down because we are reducing the capacitance of those high activity routes. We are still trying to work the existing timing margin. If we reduce the capacitance we can also attempt to reduce the drivetrain or the cell size driving that capacitance. If the capacitance is lower, the cell that is driving it doesn't need to be as big. So we can downsize, we can select a smaller cell and get even more power saved. The reason we do a good job of clock power reduction is because we are so wire centric and we understand that even based on placement what the clock tree router will do and how we can optimize that placement to give power saving.
Expand a little on incremental optimization.
Incremental optimization is different from WiresFirst. First in the sense that it is not a complete optimization of a particular block. It is more of a one cell at a time approach. We attempt to change the cell size or the cell placement. We do buffering optimization for clock tree structures. If we change any parameter we go back and verify timing. So the run time for incremental is longer and it doesn't produce as big a power saving. However some customers like it because it's small and not a complete optimization. If a customer has a particular power budget they want to hit they might want incremental optimization to reduce power with the fewest disturbances of their design.
The clock power optimization is really a placement based technique. It performs clustering of registers and tries to compact the placement of populated elements such that the clock tree routing tool will result in a shorter wire length. This is the starting point for at least four or five other things that we will be doing to reduce clock tree power consumption by looking at things clime clock tree gating. Clock power consumption is often the dominant factor and we want to concentrate on this.
We also do leakage power reduction. This particular technique with multi-Vt cell substitution is pretty well known and is not unique. We intend to do more in this area in the future.
Power Plan Gold is the other product. The real value here is productivity. This product can automatically and very quickly create complex power grid. We have a demo that we show to prospects and I literally see their eye bulge and jaws drop at how quickly a complex grid can be created. The reason we can do this so quickly is because we found a unique technology called parametric template. We use it to define power grid layouts and implement them in a design. We support multiple voltage islands and multiple power supplies. We analyze the voltage drop, power and EM in the power grid and go in and fix the voltage drop.
A complex power grid can contain rings, stripes, rails, hookups, slotting, embedded macros, complex strapping structures, non-uniform distribution and so forth. We handle these complex situations very effectively.
What about voltage islands?
There's a lot of discussion right now and a lot of people trying this methodology to reduce power consumption. Essentially what this approach says is that I can run part of my logic at a lower speed and at a lower voltage. It's a good power reduction tool but it introduces a lot of issues and challenges in the physical implementation flow. You are dealing with two different domains. It becomes more complex but it is good viable tool. Golden Gate has automated the physical implementation of voltage islands. For example we automatically insert level shifters. These are special cells that are required to exist between blocks at different power supplies to be able to translate the voltage between the two blocks. Again you have a rule based approach. We have the ability to insert level shifters and verify the proper conductivity making sure no mistake is made.
The software also knows about rings and straps and so forth. We analyze the power grid. Then we go in and surgically fix the power grid. When we detect a voltage violation, we can fix the violation by changing the power grid only in the localized area. We don't over fix the power grid because the width of power straps and power buses and so on is important because it can get in the way of signal routing. This is where you can have routing congestion. By not over fixing the power grid we are avoiding that implementation problem.
As we try to reduce the power consumption and fix the power gird we can not depend upon the final analysis tools because farming out to those tools would bring down our turn around time. So our approach is embedded integrated analysis tools such as SI and voltage drop. We use them primarily as a gauge for power reduction, voltage drop and fixing the power grid. We have good correlation with the final analysis tools but are not claiming that they are the most accurate out there. In fact we are not in the business of providing such tools. This is purely an embedded technology within power reduction.
What is the price for these tools?
Power Optimizer Gold is starting at $185K. Power Plan Gold is starting at $150K for a one year license.
Would the typical customer have one or several licenses?
Typically one license per physical designer. Companies typically try to make sure that their place and route engineers have access to their tools at all times. What we are expecting is basically as many licenses as there are P&R seats.
Do you see any direct competition.
Possibly Sequence. They traditional strength is in power analysis. Their analysis is very accurate. They are now trying to move to power reduction. Their issue specifically in the physical implementation space is that they don't have P&R technology like Golden Gate does. The best thing that they can do is provide some directives, some configuration file to traditional P&R tools but that introduces a lot of iterations. The Synopsys router may not fully understand what the Sequence configuration file is really telling them to do. It will go out and try to do whatever it needs to do. That's one disadvantage they have on power reduction side. More traditional vendors like Synopsys, Magma and Cadence claim that they do something in power reduction but they are not really focused on power. They are not coming up with unique technology. We think we can work well with whatever they provide and we can add on top of that with our technology.
Any challenges moving to 65nm and 45 nm?
It is a challenge and an opportunity for us. At 65nm and 45 nm wiring becomes even more dominant for power consumption. If we reduce wiring capacitance and optimize the interconnect we can get even higher power saving. The challenge is the complexity of design rules. That's the main challenge I see there. I was talking to an engineer who said joking that design rules at those process nodes work like this: This wire has to be so far from that wire and so far from this wire except on Tuesday when it is different. These rules are getting very complex
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