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Solido’s Recipe: Platform, Patents, Customers, Poise

Thursday, August 31st, 2017

Tags: Amit Gupta, Analog Design Automation, Deloitte, Design Automation Conference, E3 Data Science, Eric Hall, ESD Alliance, finFET, GlobalFoundries, Gloria Nichols, Jeff Dyck, Mark Gilbert, NVIDIA, Qualcomm, Samsung, Saskatoon, SOI, Solido Design Automation, Sorin Dobre, Synopsys, Ting Ku, TSMC, UX design
No Comments »

Managing Faults: OneSpin’s Dave Kelf talks ISO 26262

Tuesday, August 22nd, 2017

Tags: Bosch, Dave Kelf, formal verification, Hamming code, Infineon, ISO 26262, OneSpin
No Comments »

Fall Schedule: A Host of Must-attends

Thursday, August 17th, 2017

Tags: 2017 IEEE Photonics Conference, ARC Processor Summit 2017, ARM TechCon 2017, CDNLive, Decoding Formal Club Meeting, EDI Con 2017, EDPS 2017, ICCAD 2017, MATLAB Expo 2017, Mentor Forum 2017, TSMC OIP Ecosystem Forum
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EDPS 2017: After changes, Hidden Gem no longer

Thursday, August 3rd, 2017

Tags: EDPS, Electronic Design Process Symposium, Gary Smith, Shishpal Rawat
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Functional Safety: ISO, IEC, my Dishwasher, your Car

Wednesday, July 26th, 2017

Tags: ADAS, Anthony Seely, ASIL, Functional Safety, GE Profile Dishwasher, IEC 61508, International Electrotechnical Commission, International Organization for Standardization, ISO 26262, Karl Greb, National Electric Code
1 Comment »

Simon Davidmann: A re-energized Imperas Tutorial at DAC

Wednesday, July 19th, 2017

Tags: Agile, Altera, Cadence, CloudBees, Design Automation Conference, Imagination Technologies, Imperas, Jenkins, Linux, Simon Davidmann, Synopsys
No Comments »

Martin, Lavagno, Scheffer, Markov: Assembling a Mighty Tome for the Ages

Thursday, July 13th, 2017

Tags: Electronic Design Automation for IC Implementation Circuit Design and Process Technology, Electronic Design Automation for IC System Design Verification and Testing, Grant Martin, Igor Markov, Louis Scheffer, Luciano Lavagno
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Millennials v. Robots: The Race to destroy EDA

Wednesday, July 12th, 2017

Tags: AI, EDA, Millennials, Robots
3 Comments »

Wally Rhines: Grand Challenges in EDA

Thursday, June 8th, 2017

Tags: Grand Challenges in EDA, Mentor Graphics, Siemens, von Neumann architecture, Walden C. Rhines
1 Comment »

John Sanguinetti: Grand Challenges in EDA, Chilling Challenges in Security

Thursday, June 1st, 2017

Tags: AdaptIP, Cadence, Chronologic, CynApps, Forte Design, Grand Challenges in EDA, IoT, John Sanguinetti, Modellogic, NeXT, Peter Eichenberger, Synopsys, SystemC IDE, USB, VCS, ViewLogic, Xilinx
2 Comments »

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