Top 5 New Holiday Gifts for the Verification Engineer

Last year, we wound up in December with a post on the “Top 5 Holiday Gifts for the Verification Engineer” and it proved very popular despite the holiday timing. To refresh your memory (and ours), here is the 2013 list:

#5: Relief from hand-writing verification test code.
#4: Relief from hand-writing validation diagnostics.
#3: Vertical verification IP reuse from block to system.
#2: Horizontal verification IP reuse from electronic system level (ESL) to silicon.
#1: Effortless system coverage reflecting end-use applications.

As you might expect, every one of these gifts is still available today for users of our Trek family of products. But over the last year we have added two new products, many new features, and deeper integration into existing verification flows. So we’d like to wrap up 2014 with an all-new list of holiday gifts for the verification engineer. We hope you like them as much as you liked last year’s offerings:

#5: Easier sequence specification in UVM testbenches. Our primary focus for our graph-based scenario models has been generation of C test cases to run in multi-threaded, multiprocessor SoCs. In order to run in simulation, we have always been able to connect to the Universal Verification Methodology (UVM) verification IP models in your testbench. That allows the C test cases to send data into the chip as well as receive and check data from the chip, all in a coordinated fashion. Although many large chips are becoming SoCs,  there are still some types of hard-to-verify designs without embedded processors. Our TrekUVM product is designed specifically for these chips, running in a purely transactional UVM testbench. Users have reported to us that some types of complex sequences are easier to express with a scenario model than with the UVM alone.

#4: Faster coverage closure in UVM testbenches. When you use scenario models to describe the verification space for a chip without embedded processors, you can obtain system coverage very similar to what we generate for SoCs. We provide automated coverage closure so that you can simply indicate which nodes, paths, or cross-coverage you want to hit. TrekUVM will generate UVM test cases that are guaranteed to close the requested coverage. Some users keep other metrics (such as SystemVerilog code coverage, assertion coverage, and functional coverage) active during simulations of the TrekUVM-generated test cases. They report that closing system-level scenario coverage tends to dramatically improve the results of other forms of coverage as well.

#3: Integration of system coverage with other coverage metrics. Verification teams now have several forms of coverage metrics available to them. All the simulation vendors provide some form of roll-up that combines all these metrics, possibly with user-selected weighting, into a single coverage percentage for the entire chip. We have added the option to generate SystemVerilog coverage groups that reflect the system coverage achieved in our scenario models. Since our unique coverage is available in a standard format, you can easily read it into any coverage viewer and roll it up with your other metrics.

We have validated this flow with multiple simulators and the Synopsys open Verdi debug solution. Note that this same flow works for system coverage obtained from TrekUVM in a transactional testbench or TrekSoC running C test cases in a simulation or acceleration environment. In fact, system coverage from TrekSoC-Si running test cases on a hardware platform can be combined with coverage results from the same design running in simulation.

#2: Debug of automatic test cases using standard tools. When you run a test case generated by one of our Trek family of products, it may fail. This may be due to an error in the chip design itself, an error in your testbench, or an error in your scenario model. When such an error occurs, you want to debug it using the same technology you would use for one of your own hand-written tests. We are well integrated with industry-leading platforms such as the Synopsys Verdi HW SW debug solution, the ARM DS-5 Development Studio, and Carbon Performance Analysis Kits (CPAKs).

#1: A fully automated solution for cache coherency verification. Our new TrekApp family provides pre-built scenario models to solve specific verification challenges without the need to learn about graphs. The first available member of this family is our Coherency TrekApp, which works with TrekSoC or TrekSoC-Si to generate test cases for multiprocessor, multi-level cache-based systems. You simply provide some basic information on the configuration of your processors, memories, and caches, and we do the rest of the work.

Once gain, all five gifts are automatic benefits from our scenario model approach. For about the same effort as hand-writing one simulation test case or one validation diagnostic, we or you can develop a vertically and horizontally reusable scenario model capable of generating hundreds or thousands of test cases and providing system coverage that combines with other metrics. Your local Breker sales representative will be happy to provide these gifts to you in exchange for a modest investment on your part. Thanks for reading, and Happy Holidays!

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Breker, coherency, coverage, EDA, functional verification, graph, reuse, scenario model, simulation, SoC, SoC verification, system coverage, test generation, transactional, TrekSoC, TrekSoC-Si, TrekUVM, use cases, uvm, verification IP, VIP

This entry was posted on Tuesday, December 30th, 2014 at 5:40 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.