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Wednesday, November 7th, 2012
Tags: Atrenta, Chip Design, Constellations 2012, EDA, Electronic Design Automation, IP, IP standards, IPextreme, Semiconductor IP, soft IP
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Thursday, October 25th, 2012
Tags: A/MS, analog mixed-signal, Atrenta, Chip Design, EDA, Electronic Design Automation, finite state machines, Low-Power High-Performance Engineering Community, NextOP, semiconductors, SoC, SpyGlass, verification
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Wednesday, October 10th, 2012
Tags: Atrenta, Brian Bailey, CDC, CPF, EDA, EDA DesignLine, EE Times, low power, Power awareness, power domains, register transfer level, RTL, semiconductors, SoC, UPF, verification
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Wednesday, October 3rd, 2012
Tags: Atrenta, CDC, CDC verification, Chip Design, Clock Domain, EDA, EDA DesignLine, EE Times, Electronic Design Automation, Network on Chip, NoC, semiconductors, SoC, System on Chip
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Tuesday, September 4th, 2012
Tags: Ajoy Bose, Atrenta, Chip Design, EDA, Electronic Design Automation, Jim Hogan, National Institute of Technology, RTL, semiconductors, SoC, System Design, System on Chip
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Monday, August 20th, 2012
Tags: Atrenta, Chip Design, EDA, Electronic Design Automation, Nikkei, register transfer level, Renesas, RTL, Semiconductor IP, semiconductors, SoC, SpyGlass, SpyGlass Physical, System on Chip, Tech-On
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Wednesday, August 8th, 2012
Tags: Atrenta, EDA, EE Daily News, Electronic Design Automation, Finance, investments, Mike Demler. Semiconductors, RTL, Semiconductor IP, Springsoft, Synopsys
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