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 Real Talk  by Graham Bell
Graham Bell
#2 on GarySmithEDA What to See @ DAC List – Why?
The last two weeks before the Design Automation Conference in San Francisco are a busy time.  For us marketeers, it has been called "our Superbowl."  We want to get the word out that we have something new and important to show visitors to at our …

 Guest Blogger  by Anne Cirkel
Anne Cirkel
Why the DAC Designer Track is the best deal in town
Memorial Day has come and gone, which means two things: summer is here and DAC is officially upon us. In just over a week the doors will open at Moscone Center with a blockbuster designer keynote: Brian Otis, director of Google’s smart contact …

 The Breker Trekker  by Tom Anderson, VP of Marketing
Tom Anderson, VP of Marketing
Portable Stimulus Layer 3: Test Randomization
Over the lifetime of this blog, we've covered a lot of diverse topics regarding Breker's products and technology, trends in SoC verification, and the EDA industry in general. For the last month, we've offered our longest series of posts ever on a …

 What's PR got to do with it?  by Ed Lee
Ed Lee
Design rules built on quicksand?
  Sage CEO Coby Zelnik recently talked with us about how design rules need a formal methodology to account for all the permutations of each rule for today’s and the next generation’s chip designs. What I found alarming was that he …

 Memory Pill  by Gustavo Litovsky
Gustavo Litovsky
Bluetooth Low-Energy Differentiation Through Cost Trade-Offs
Bluetooth Low Energy (BLE) –– or Bluetooth SMART as it’s marketed by most vendors –– is rapidly making its way into all kinds of new products. Its adoption has opened the floodgates to a slew of new devices. With support for Bluetooth …

 Core Values  by Neil Parris
Neil Parris
From months to days: an IP integration innovation at 52DAC
Some innovations give such an exponential productivity shift that they are often only appreciated when viewed with the perspective of history. Isambard Kingdom Brunel built the first train line from London to Bristol and cut down the travel times …

 What Would Joe Do?  by Peggy Aycinena
Peggy Aycinena
Tortuga Logic: Expect the Unexpected
  If you're a Spanish speaker, the first image that comes to mind when someone says tortuga is a slow-moving animal in a shell. Alternatively, if you're a kid at heart and love pirates, the first image that comes to mind when someone says …

 IP Showcase  by Peggy Aycinena
Peggy Aycinena
Innovation: Thy name is eSilicon
  While news last week out of eSilicon proved again the company's ability to innovate and build on emerging technologies, a phone call with company VP Mike Gianfagna also proved something: Mike continues to be one of the ablest spokesmen in …

 Embedded Software  by Colin Walls
Colin Walls
Using an MMU
Many microprocessors and microcontrollers incorporate a memory management unit (MMU) or have one available as an option. Equally, there are some devices that have no MMU support and many systems are built without one anyway. Having met some …

 Aldec Design and Verification  by Satyam Jani
Satyam Jani
The Pythonic Tonic: Miracle cure or Snake-oil?
Python is making inroads in the EDA landscape, but is all the hype justified? Do the productivity benefits of a dynamic language translate to gains for real-world development for ASIC and FPGA designs? Chris Higgs of Potential Ventures will be …

 Decoding Formal  by Dr. Jin Zhang
Dr. Jin Zhang
Preparing for Another Challenge at DAC: Break the Testbench!
You may remember the Oski Technology Live Verification Challenge in 2012, where during the 72 hours of DAC, Oski verification engineer Chirag Agarwal formally verified a well-simulated design from NVIDIA, sight unseen, live and on camera, and found …

 EDA Careers Corner  by Mark Gilbert
Mark Gilbert
Where Might Technology Be Taking Us, I Get A Little Crazy with Mentor’s CEO, Part 3 of My Amazing Must Read Wally Interview… How Was DVCON
DVCON was, well, DVCON…nothing out of the ordinary; it was as always well-attended with good traffic, perhaps even more than I have seen previously. The one good thing I noticed, and this is technically very important: the food and drink is …

 Disrupted Hard  by Matthieu Wipliez
Matthieu Wipliez
Numbers don’t lie: there is virtually no interest in high level synthesis
I finally read enough articles about high level synthesis (HLS) that give a sense of hype that just didn't seem to be matched by what I've heard. Now hype is pretty subjective, but numbers are not. For example, the High Level Synthesis group on …

 Video Roundup  by Sanjay Gangal
Sanjay Gangal
NVIDIA’s press event at the International Consumer Electronics Show 2015 in Las Vegas
Here is a playlist of the Nvidia's press event at the CES 2015. The playlist has 9 …

 ExcelliBlog  by Rick Eram, Sales & Marketing VP
Rick Eram, Sales & Marketing VP
Value of timing constraints files beyond STA
Timing Constraint files are one of the best timing and clock data containers available to the designers, yet they are under utilized today and their value is not fully exploited in the design flow. The timing information captured in timing …

 The Instigater: Services with a Smile  by Arman Poghosyan
Arman Poghosyan
EDA Application Porting Guide: Part 1
Introduction With this article we would like to start a series of tutorials covering the migration of EDA applications from Windows to Mac OS X and GNU/Linux. For that purpose we will review the technologies for building user-interface, data layer …

 The Dominion of Design  by Sanjay Gangal
Sanjay Gangal
Asymptotic or Divergent: Three Verification Managers Look to the Future at DAC
What would the Design Automation Conference (DAC) be without a verification panel or two? This year, one in particular takes a look at a variety of verification technologies. Titled, “The Asymptote of Verification,” it will be moderated by Bryon …

 ASIC with Ankit  by Ankit Gopani
Ankit Gopani
Class – The Classic Feature – Part II
Dear AWA Readers Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test …

 NOT EDA  by Sanjay Gangal
Sanjay Gangal
Satya Nadella Named Microsoft CEO
Article source: Microsoft Corp. & Wikipedia Microsoft Corp. today announced that its Board of Directors has appointed Satya Nadella as Chief Executive Officer and member of the Board of Directors effective immediately. Nadella previously …

 Analog Insights  by Hélène Thibiéroz
Hélène Thibiéroz
Optimized Synopsys-MathWorks solution for System-Level Verification
Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, …

 It's Verific !  by Michiel Ligthart
Michiel Ligthart
The demise of VHDL has been greatly exaggerated
I don’t recall when it was the first time that I heard VHDL was a dying language, but for sure it was many years ago, maybe as far back as the late 1990s. Obviously the EDA futurists of then got it very wrong, and I was recently wondering if I …

 AWR Insights  by Sherry Hess
Sherry Hess
AWR: Redefining Design
When I first learned of NI’s Redefining campaign, I thought… yes, makes perfect sense and fits AWR extremely well. Our company was founded almost 20 years ago on the very idea of redefining design for microwave/RF engineers. We began this …

 Dispatches from Boston  by Nanette Collins
Nanette Collins
OneSpin Reaches for the Cloud
As the 50th Design Automation Conference opens, attendees rushing through the doors early Monday may have their heads in a Cloud. Cloud computing that is, and heading straight toward Booth #846. That’s because OneSpin Solutions in Booth #846 …

 Verification is No Simulation  by Dave Rich
Dave Rich
Get your IEEE 1800-2012 SystemVerilog LRM at no charge
At this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge …

 Industry Commentary  by Dr. Russ Henke
Dr. Russ Henke
The EDA and MCAD/MCAE Almanac – Nominal Q3 2012 Part B: MCAD/MCAE Industry
Dear faithful blog reader: Please take a few minutes of your valuable time to read the January 31, 2013 article, “The EDA and MCAD/MCAE Almanac - Nominal Q3 2012 Part B: MCAD/MCAE Industry” You may reach the new January 31 Commentary by …

 IEEE CEDA Corner  by Joel Phillips
Joel Phillips
Alberto Sangiovanni-Vincentelli Celebrates ICCAD’s 30th Anniversary with Look Back at EDA
CEDA turned to Alberto Sangiovanni-Vincentelli of the University of California, Berkeley, to help us celebrate the 30 anniversary of the International Conference in Computer-Aided Design (ICCAD). And, he didn’t disappoint. In a rousing talk …

 Gabe's EDA Update  by Gabe Moretti
Gabe Moretti
The Approaching Discontinuity
The world of EDA is about to change. The subtle signs are there for all to see, and the coming reality is so different to be scary to some. Thus better not to talk about it. The changes will include how ICs are designed, developed, and verified. …

 CynCity  by Brett Cline
Brett Cline
A Profile of Forte Design Systems
Russ Henke, a contributing editor at EDACafe, recently profiled Forte. We’re repurposing it here in its entirety because we think it’s an accurate depiction of where we’ve come and what we’ve accomplished. We hope you like it as much as …

 ForEVEr  by Mitsuhiro Matsumoto
Mitsuhiro Matsumoto
A Practical Approach to Chip-level Assertion-Based Verification
Are you using assertions in your logic verification? Assertion-based verification is rapidly gaining popularity as a methodology for more efficient SoC debugging. Both HDL simulators and property-based formal verification tools are recognized as …

 EDA Thoughts  by Daniel Payne
Daniel Payne
DAC 2011 Trip Reports – Mostly Transistor Level Tools
2011 was the year of the foundry (TSMC, Globalfoundries, Samsung) at DAC in San Diego. The foundries had bigger booths, bigger events, were on more panel sessions, and had more marketing influence than any other year that I can remember. The …

 Global Business in EDA  by Mo Casas
Mo Casas
Are you missing the opportunity to go global? These tips will signal if you are ready
Expanding business overseas is important. If you are a small EDA vendor, going global before you are ready can be suicidal. Here are some signals that can help you decide you if you are ready to go global. Have you been successful at …

 Become Your Customers  by Saranyan Vigraham

 Open Electrons  by Chitlesh Goorah (Free Electronic Lab)
Chitlesh Goorah (Free Electronic Lab)
Milkymist: pushing further the limits of electronics openness
Everyone has heard of open source software, but can the same principles be applied to hardware? Some people argue that hardware is so expensive to manufacture and modify that it prevents hobbyists from contributing, and thus stifles …

 Stan on Standards  by Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski, Group Director of Standards, Cadence
Japan & SystemC
With all of the excitement in the “front end” of the SOC design/verification/modeling community about Accellera’s UVM, it is easy to loose track of work being done around another significant front end language—SystemC.  For those not aware, …

 Thursday's Child  by Peggy Aycinena
Peggy Aycinena
X-FAB: High-temp mission profile
Headquartered in Germany, X-FAB is a foundry with manufacturing operations in Erfurt and Dresden, Plymouth in the U.K., Lubbock in Texas, and Kuching, Sarawak in Malaysia. On September 8th, X-FAB made an interesting announcement with the …

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Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Tortuga Logic: Expect the Unexpected
Peggy AycinenaIP Showcase
by Peggy Aycinena
Innovation: Thy name is eSilicon
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