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 Real Talk  by Dr. Pranav Ashar
Dr. Pranav Ashar
The Future of 3D Technologies is Fast and Heterogeneous
With the slow down in Moore's law, technologists are now speculating on what future integrated circuits will look like.  One constraint is the clock frequency of CMOS processors,  which is topping out at around 4GHz for high-end processors in the …

 Aldec Design and Verification  by Louie De Luna
Louie De Luna
Developing high-reliability FPGAs for DO-254
You have been developing FPGAs for a long time, and you know your designs from top to bottom. You know every interface protocol, configuration and optimization. You can visualize your timing diagram like you can visualize your upcoming vacation in …

 The Breker Trekker  by Tom Anderson, VP of Marketing
Tom Anderson, VP of Marketing
Are Verification and Validation Different? Does Anyone Care?
For the most part, the terms "verification" and "validation" are used interchangeably in the electronics industry. However, there are many who argue that these are distinct activities in the development of SoC s and systems, performed at different …

 What Would Joe Do?  by Peggy Aycinena
Peggy Aycinena
Kaufman Award: My vote goes to Wally
  As you all know, the Kaufman Award is presented every 12 to 18 months by the EDA industry, with support from the EDA Consortium and the IEEE Council on EDA. Year in and year out, an individual from industry or academia is honored for …

 IP Showcase  by Peggy Aycinena
Peggy Aycinena
DOCEA Power: What’s the scoop?
  When it comes to Docea Power, there's no scoop. There's no news at all. Except of course that they've been bought by Intel, which in itself is pretty big news for any company. Except apparently Docea. There was/is no press release and …

 Embedded Software  by Colin Walls
Colin Walls
When compilers do magic
What is a compiler? Ask an average engineer and you will get an answer something like: “A software tool that translates high level language code into assembly language or machine code.” Although this definition is not incorrect, it is rather …

 Decoding Formal  by Dr. Jin Zhang
Dr. Jin Zhang
Oski on the Bay in San Francisco
EDA’s verification market segment is not the only place where something’s named for the Cal (University of California, Berkeley) mascot Oski. A Blue and Gold Fleet boat named Oski sails out of Pier 39 in San Francisco and takes visitors around …

 EDA Careers Corner and News  by Mark Gilbert
Mark Gilbert
EDA Offers Incredible Longevity…CRITICAL, What makes a GREAT Resume
EDA, Electronic Design Automation gets its share of getting kicked around. After all, since the Internet boom (or some might say bust), the Social Media boom, Analytics boom, and Big Data boom, several alternatives to EDA have had significant impact …

 Core Values  by Neil Parris
Neil Parris
7 things I learned at 52DAC
Last week I attended the Design Automation Conference as an intrepid reporter to put my ear to the ground and take note of what is happening in the industry. I wrote some daily review blogs of my time on the show floor (which can be seen here, Day …

 Memory Pill  by Bruce Kleinman
Bruce Kleinman
IoT Security Cannot Afford To Be an Oxymoron
Bruce Kleinman Principal FSVadvisors www.fsvadvisors.com Securing the Internet of Things (IoT) presents opportunities and challenges. IoT security has seen far more press coverage, to date, than actual delivered solutions. The dearth of secure …

 Guest Blogger  by Anne Cirkel
Anne Cirkel
Why the DAC Designer Track is the best deal in town
Memorial Day has come and gone, which means two things: summer is here and DAC is officially upon us. In just over a week the doors will open at Moscone Center with a blockbuster designer keynote: Brian Otis, director of Google’s smart contact …

 What's PR got to do with it?  by Ed Lee
Ed Lee
Design rules built on quicksand?
  Sage CEO Coby Zelnik recently talked with us about how design rules need a formal methodology to account for all the permutations of each rule for today’s and the next generation’s chip designs. What I found alarming was that he …

 Disrupted Hard  by Matthieu Wipliez
Matthieu Wipliez
Numbers don’t lie: there is virtually no interest in high level synthesis
I finally read enough articles about high level synthesis (HLS) that give a sense of hype that just didn't seem to be matched by what I've heard. Now hype is pretty subjective, but numbers are not. For example, the High Level Synthesis group on …

 Video Roundup  by Sanjay Gangal
Sanjay Gangal
NVIDIA’s press event at the International Consumer Electronics Show 2015 in Las Vegas
Here is a playlist of the Nvidia's press event at the CES 2015. The playlist has 9 …

 ExcelliBlog  by Rick Eram, Sales & Marketing VP
Rick Eram, Sales & Marketing VP
Value of timing constraints files beyond STA
Timing Constraint files are one of the best timing and clock data containers available to the designers, yet they are under utilized today and their value is not fully exploited in the design flow. The timing information captured in timing …

 The Instigater: Services with a Smile  by Arman Poghosyan
Arman Poghosyan
EDA Application Porting Guide: Part 1
Introduction With this article we would like to start a series of tutorials covering the migration of EDA applications from Windows to Mac OS X and GNU/Linux. For that purpose we will review the technologies for building user-interface, data layer …

 The Dominion of Design  by Sanjay Gangal
Sanjay Gangal
Asymptotic or Divergent: Three Verification Managers Look to the Future at DAC
What would the Design Automation Conference (DAC) be without a verification panel or two? This year, one in particular takes a look at a variety of verification technologies. Titled, “The Asymptote of Verification,” it will be moderated by Bryon …

 ASIC with Ankit  by Ankit Gopani
Ankit Gopani
Class – The Classic Feature – Part II
Dear AWA Readers Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test …

 NOT EDA  by Sanjay Gangal
Sanjay Gangal
Satya Nadella Named Microsoft CEO
Article source: Microsoft Corp. & Wikipedia Microsoft Corp. today announced that its Board of Directors has appointed Satya Nadella as Chief Executive Officer and member of the Board of Directors effective immediately. Nadella previously …

 Analog Insights  by Hélène Thibiéroz
Hélène Thibiéroz
Optimized Synopsys-MathWorks solution for System-Level Verification
Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, …

 It's Verific !  by Michiel Ligthart
Michiel Ligthart
The demise of VHDL has been greatly exaggerated
I don’t recall when it was the first time that I heard VHDL was a dying language, but for sure it was many years ago, maybe as far back as the late 1990s. Obviously the EDA futurists of then got it very wrong, and I was recently wondering if I …

 AWR Insights  by Sherry Hess
Sherry Hess
AWR: Redefining Design
When I first learned of NI’s Redefining campaign, I thought… yes, makes perfect sense and fits AWR extremely well. Our company was founded almost 20 years ago on the very idea of redefining design for microwave/RF engineers. We began this …

 Dispatches from Boston  by Nanette Collins
Nanette Collins
OneSpin Reaches for the Cloud
As the 50th Design Automation Conference opens, attendees rushing through the doors early Monday may have their heads in a Cloud. Cloud computing that is, and heading straight toward Booth #846. That’s because OneSpin Solutions in Booth #846 …

 Verification is No Simulation  by Dave Rich
Dave Rich
Get your IEEE 1800-2012 SystemVerilog LRM at no charge
At this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge …

 Industry Commentary  by Dr. Russ Henke
Dr. Russ Henke
The EDA and MCAD/MCAE Almanac – Nominal Q3 2012 Part B: MCAD/MCAE Industry
Dear faithful blog reader: Please take a few minutes of your valuable time to read the January 31, 2013 article, “The EDA and MCAD/MCAE Almanac - Nominal Q3 2012 Part B: MCAD/MCAE Industry” You may reach the new January 31 Commentary by …

 IEEE CEDA Corner  by Joel Phillips
Joel Phillips
Alberto Sangiovanni-Vincentelli Celebrates ICCAD’s 30th Anniversary with Look Back at EDA
CEDA turned to Alberto Sangiovanni-Vincentelli of the University of California, Berkeley, to help us celebrate the 30 anniversary of the International Conference in Computer-Aided Design (ICCAD). And, he didn’t disappoint. In a rousing talk …

 Gabe's EDA Update  by Gabe Moretti
Gabe Moretti
The Approaching Discontinuity
The world of EDA is about to change. The subtle signs are there for all to see, and the coming reality is so different to be scary to some. Thus better not to talk about it. The changes will include how ICs are designed, developed, and verified. …

 CynCity  by Brett Cline
Brett Cline
A Profile of Forte Design Systems
Russ Henke, a contributing editor at EDACafe, recently profiled Forte. We’re repurposing it here in its entirety because we think it’s an accurate depiction of where we’ve come and what we’ve accomplished. We hope you like it as much as …

 ForEVEr  by Mitsuhiro Matsumoto
Mitsuhiro Matsumoto
A Practical Approach to Chip-level Assertion-Based Verification
Are you using assertions in your logic verification? Assertion-based verification is rapidly gaining popularity as a methodology for more efficient SoC debugging. Both HDL simulators and property-based formal verification tools are recognized as …

 EDA Thoughts  by Daniel Payne
Daniel Payne
DAC 2011 Trip Reports – Mostly Transistor Level Tools
2011 was the year of the foundry (TSMC, Globalfoundries, Samsung) at DAC in San Diego. The foundries had bigger booths, bigger events, were on more panel sessions, and had more marketing influence than any other year that I can remember. The …

 Global Business in EDA  by Mo Casas
Mo Casas
Are you missing the opportunity to go global? These tips will signal if you are ready
Expanding business overseas is important. If you are a small EDA vendor, going global before you are ready can be suicidal. Here are some signals that can help you decide you if you are ready to go global. Have you been successful at …

 Become Your Customers  by Saranyan Vigraham

 Open Electrons  by Chitlesh Goorah (Free Electronic Lab)
Chitlesh Goorah (Free Electronic Lab)
Milkymist: pushing further the limits of electronics openness
Everyone has heard of open source software, but can the same principles be applied to hardware? Some people argue that hardware is so expensive to manufacture and modify that it prevents hobbyists from contributing, and thus stifles …

 Stan on Standards  by Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski, Group Director of Standards, Cadence
Japan & SystemC
With all of the excitement in the “front end” of the SOC design/verification/modeling community about Accellera’s UVM, it is easy to loose track of work being done around another significant front end language—SystemC.  For those not aware, …

EMA: OrCAD 16.6 - 2015 30th Anniversary release

Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Kaufman Award: My vote goes to Wally
Peggy AycinenaIP Showcase
by Peggy Aycinena
DOCEA Power: What’s the scoop?
More Editorial  
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