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 The Breker Trekker  by Tom Anderson, VP of Marketing
Tom Anderson, VP of Marketing
The Ever-Changing EDA Landscape
In last week's post on The Breker Trekker blog, we surveyed the semiconductor market for the past 15 years or so from the standpoint of revenue leadership. Wikipedia provides a set of  tables showing the top 20 semiconductor vendors for each year. …

 Embedded Software  by Colin Walls
Colin Walls
OS influence on power consumption
Power consumption is an issue. With portable devices this affects battery life. [I am irritated by the short intervals between necessary charging sessions with my smartphone, for example.] With mains powered equipment, power consumption is also a …

 What Would Joe Do?  by Peggy Aycinena
Peggy Aycinena
Dr. Rhines: EDA’s charm & intelligence reflected in Q4_2014
  Quarterly, as many of you know, the Market Statistics Service of the EDA Consortium reports out on the health of the industry. Quarterly, as well, Mentor CEO Dr. Walden Rhines makes himself available to the Press, to comment and elaborate …

 EDA Careers Corner  by Mark Gilbert
Mark Gilbert
Where Might Technology Be Taking Us, I Get A Little Crazy with Mentor’s CEO, Part 3 of My Amazing Must Read Wally Interview… How Was DVCON
DVCON was, well, DVCON…nothing out of the ordinary; it was as always well-attended with good traffic, perhaps even more than I have seen previously. The one good thing I noticed, and this is technically very important: the food and drink is …

 Disrupted Hard  by Matthieu Wipliez
Matthieu Wipliez
Numbers don’t lie: there is virtually no interest in high level synthesis
I finally read enough articles about high level synthesis (HLS) that give a sense of hype that just didn't seem to be matched by what I've heard. Now hype is pretty subjective, but numbers are not. For example, the High Level Synthesis group on …

 Core Values  by Neil Parris
Neil Parris
Extended System Coherency Part 3: Increasing Performance and Introducing CoreLink CCI-500
  System coherency remains an important factor for SoC design starts. The ARM® CoreLink™ CCI-400 has seen great success, over 35 licensees across multiple applications from mobile big.LITTLE, to network infrastructure, digital TV and …

 Real Talk  by Graham Bell
Graham Bell
High-Level Synthesis: New Driver for RTL Verification
In a recent blog, Does Your Synthesis Code Play Well With Others?,  I explored some of the requirements for verifying the quality of the RTL code generated by high-level synthesis (HLS) tools.  At a minimum, a state-of-the-art lint tool should be …

 Decoding Formal  by Dr. Jin Zhang
Dr. Jin Zhang
“Shift Left” with Formal Technology
“Shift Left” has become a hot phrase after Aart’s keynote speech at DVCon2015 where he talked about how shifting left in schedule resulted from 10x productivity gain in design, IP, verification and software can spur on 100x opportunities in …

 IP Showcase  by Peggy Aycinena
Peggy Aycinena
DesignWare EV IP: Convolutional Neural Networks at Core of Capabilities
  Early Monday morning, Synopsys announced several new bits have been added to their impressive bucket of IP blocks, a new family of DesignWare processors targeted at vision applications. With an honorable pedigree – descent from the ARC …

 Guest Blogger  by Anne Cirkel
Anne Cirkel
Seeds of a great conference: Keynote superstars and stellar refereed content at DAC 52
Nose around the design automation industry a bit and you’re sure to find mention of the goal to “shift left.” Basically the idea is to try to solve problems and add value earlier in the design cycle. Engineers usually first stitch together …

 What's PR got to do with it?  by Ed Lee
Ed Lee
S parameters have to be accurate…does in-situ de-embedding work?
If you're a board engineer, are you encountering high-speed issues? What are they? One that's garnering some thinking and observer attention is signal integrity for high(er) speed board designs. With most all designs running at 10 Gbps (more …

 Aldec Design and Verification  by Stan Hanel
Stan Hanel
Are Metastability Monsters Lurking Beneath the Surface?
Every engineer and technician is aware of Murphy’s Law: “Anything that can go wrong will go wrong”. The law appears when your elegantly-sculpted hardware and artfully-styled software code bang up against the real world of transition delays …

 Memory Pill  by Ron Moore
Ron Moore
Optimized SRAM Critical to SoCs in Hot Market Segments
Ron Moore Vice President of Marketing ARM Physical Design Group According to industry analysts, SRAM design is designated as Foundation IP and considered by most to be commodity IP available from multiple suppliers. Standard cell libraries and …

 Video Roundup  by Sanjay Gangal
Sanjay Gangal
NVIDIA’s press event at the International Consumer Electronics Show 2015 in Las Vegas
Here is a playlist of the Nvidia's press event at the CES 2015. The playlist has 9 …

 ExcelliBlog  by Rick Eram, Sales & Marketing VP
Rick Eram, Sales & Marketing VP
Value of timing constraints files beyond STA
Timing Constraint files are one of the best timing and clock data containers available to the designers, yet they are under utilized today and their value is not fully exploited in the design flow. The timing information captured in timing …

 The Instigater: Services with a Smile  by Arman Poghosyan
Arman Poghosyan
EDA Application Porting Guide: Part 1
Introduction With this article we would like to start a series of tutorials covering the migration of EDA applications from Windows to Mac OS X and GNU/Linux. For that purpose we will review the technologies for building user-interface, data layer …

 The Dominion of Design  by Sanjay Gangal
Sanjay Gangal
Asymptotic or Divergent: Three Verification Managers Look to the Future at DAC
What would the Design Automation Conference (DAC) be without a verification panel or two? This year, one in particular takes a look at a variety of verification technologies. Titled, “The Asymptote of Verification,” it will be moderated by Bryon …

 ASIC with Ankit  by Ankit Gopani
Ankit Gopani
Class – The Classic Feature – Part II
Dear AWA Readers Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test …

 NOT EDA  by Sanjay Gangal
Sanjay Gangal
Satya Nadella Named Microsoft CEO
Article source: Microsoft Corp. & Wikipedia Microsoft Corp. today announced that its Board of Directors has appointed Satya Nadella as Chief Executive Officer and member of the Board of Directors effective immediately. Nadella previously …

 Analog Insights  by Hélène Thibiéroz
Hélène Thibiéroz
Optimized Synopsys-MathWorks solution for System-Level Verification
Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, …

 It's Verific !  by Michiel Ligthart
Michiel Ligthart
The demise of VHDL has been greatly exaggerated
I don’t recall when it was the first time that I heard VHDL was a dying language, but for sure it was many years ago, maybe as far back as the late 1990s. Obviously the EDA futurists of then got it very wrong, and I was recently wondering if I …

 AWR Insights  by Sherry Hess
Sherry Hess
AWR: Redefining Design
When I first learned of NI’s Redefining campaign, I thought… yes, makes perfect sense and fits AWR extremely well. Our company was founded almost 20 years ago on the very idea of redefining design for microwave/RF engineers. We began this …

 Dispatches from Boston  by Nanette Collins
Nanette Collins
OneSpin Reaches for the Cloud
As the 50th Design Automation Conference opens, attendees rushing through the doors early Monday may have their heads in a Cloud. Cloud computing that is, and heading straight toward Booth #846. That’s because OneSpin Solutions in Booth #846 …

 Verification is No Simulation  by Dave Rich
Dave Rich
Get your IEEE 1800-2012 SystemVerilog LRM at no charge
At this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge …

 Industry Commentary  by Dr. Russ Henke
Dr. Russ Henke
The EDA and MCAD/MCAE Almanac – Nominal Q3 2012 Part B: MCAD/MCAE Industry
Dear faithful blog reader: Please take a few minutes of your valuable time to read the January 31, 2013 article, “The EDA and MCAD/MCAE Almanac - Nominal Q3 2012 Part B: MCAD/MCAE Industry” You may reach the new January 31 Commentary by …

 IEEE CEDA Corner  by Joel Phillips
Joel Phillips
Alberto Sangiovanni-Vincentelli Celebrates ICCAD’s 30th Anniversary with Look Back at EDA
CEDA turned to Alberto Sangiovanni-Vincentelli of the University of California, Berkeley, to help us celebrate the 30 anniversary of the International Conference in Computer-Aided Design (ICCAD). And, he didn’t disappoint. In a rousing talk …

 Gabe's EDA Update  by Gabe Moretti
Gabe Moretti
The Approaching Discontinuity
The world of EDA is about to change. The subtle signs are there for all to see, and the coming reality is so different to be scary to some. Thus better not to talk about it. The changes will include how ICs are designed, developed, and verified. …

 CynCity  by Brett Cline
Brett Cline
A Profile of Forte Design Systems
Russ Henke, a contributing editor at EDACafe, recently profiled Forte. We’re repurposing it here in its entirety because we think it’s an accurate depiction of where we’ve come and what we’ve accomplished. We hope you like it as much as …

 ForEVEr  by Mitsuhiro Matsumoto
Mitsuhiro Matsumoto
A Practical Approach to Chip-level Assertion-Based Verification
Are you using assertions in your logic verification? Assertion-based verification is rapidly gaining popularity as a methodology for more efficient SoC debugging. Both HDL simulators and property-based formal verification tools are recognized as …

 EDA Thoughts  by Daniel Payne
Daniel Payne
DAC 2011 Trip Reports – Mostly Transistor Level Tools
2011 was the year of the foundry (TSMC, Globalfoundries, Samsung) at DAC in San Diego. The foundries had bigger booths, bigger events, were on more panel sessions, and had more marketing influence than any other year that I can remember. The …

 Global Business in EDA  by Mo Casas
Mo Casas
Are you missing the opportunity to go global? These tips will signal if you are ready
Expanding business overseas is important. If you are a small EDA vendor, going global before you are ready can be suicidal. Here are some signals that can help you decide you if you are ready to go global. Have you been successful at …

 Become Your Customers  by Saranyan Vigraham

 Open Electrons  by Chitlesh Goorah (Free Electronic Lab)
Chitlesh Goorah (Free Electronic Lab)
Milkymist: pushing further the limits of electronics openness
Everyone has heard of open source software, but can the same principles be applied to hardware? Some people argue that hardware is so expensive to manufacture and modify that it prevents hobbyists from contributing, and thus stifles …

 Stan on Standards  by Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski, Group Director of Standards, Cadence
Japan & SystemC
With all of the excitement in the “front end” of the SOC design/verification/modeling community about Accellera’s UVM, it is easy to loose track of work being done around another significant front end language—SystemC.  For those not aware, …

 Thursday's Child  by Peggy Aycinena
Peggy Aycinena
X-FAB: High-temp mission profile
Headquartered in Germany, X-FAB is a foundry with manufacturing operations in Erfurt and Dresden, Plymouth in the U.K., Lubbock in Texas, and Kuching, Sarawak in Malaysia. On September 8th, X-FAB made an interesting announcement with the …


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