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 The Breker Trekker  by Tom Anderson, VP of Marketing
Tom Anderson, VP of Marketing
Merger Mania in the Semiconductor Industry
Earlier this year, we published an analysis of the semiconductor landscape that became one of the most-read posts in the history of The Breker Trekker. That's not too surprising, since business topics tend to have wider appeal than detailed …

 EDAC Connected  by Bob Smith, Executive Director
Bob Smith, Executive Director
An Evening on Patents
Talking about patents at a cocktail party is no way to make friends and a near-perfect way to clear    the room! Nonetheless, the EDA Consortium is about to take that risk as we kick off our new Legal Series with a panel, “Patents and Patent …

 EDA Careers Corner and News  by Mark Gilbert
Mark Gilbert
The Must-Read Interviewing Guide For Candidates and Hiring Managers…How Both Sides Can Win In An Interview!
This is a crucial column that every candidate and hiring manager should read so they can each wisely get the most out of the interviewing process. First to the candidates… Acing an interview these days is incredibly difficult. Sometimes, your …

 Video Roundup  by Susan Smith
Susan Smith
HP Announces HP Z240 Tower and Z240 SFF Workstations
Jeff Wood - vice president, WW Product Management,  Workstation and Thin Client Business HP and Josh Peterson- director, WW Product Management,  Workstation and Thin Client Business , HP met with the press in a virtual press briefing prior to the …

 Real Talk  by Lisa Piper, Technical Marketing Manager at Real Intent
Lisa Piper, Technical Marketing Manager at Real Intent
Correcting Pessimism without Optimism – Part Two
Part one of this article focused on the issues of X-pessimism at the netlist level and why the current solutions are inadequate.  In In part two, we look at how the Ascent XV tool correctly addresses X-safe verification. If a node is determined …

 What Would Joe Do?  by Peggy Aycinena
Peggy Aycinena
Andrew Kahng: Modeling the Future of Semiconductors (and Test)
  Andrew Kahng is Professor of CSE and ECE at UC San Diego, and former General Chair at DAC, ISQED, and ISPD. As such, he knows what people who attend conferences need to hear. Next week he's taking that knowledge to IEEE's International …

 IP Showcase  by Peggy Aycinena
Peggy Aycinena
Answer’s nope: Should EDA Consortium become IP Consortium?
  The news is good out of EDA this week: The industry continues up and to the right. EDAC's Market Statistic Services produced the numbers: "The EDA industry revenue increased 8.5 percent for Q2 2015 to $1906.5 million, compared to …

 Hardware Emulation Journal  by Lauro Rizzatti
Lauro Rizzatti
Classic Operas & Hardware Emulation
Recently, I read a quote from Peter G. Davis from The New York Times in 2007, who wrote: “’Cosi` fan tutte’ was virtually unknown a half-century ago, considered a trivial farce scarcely worth reviving. Now it is admired as one of Mozart’s …

 Decoding Formal  by Pippa Slayton
Pippa Slayton
Happy Birthday, Decoding Formal!
On the radio yesterday, we heard that the song “Happy Birthday To You”, one of the most widely sung tunes in the world, was ruled by federal judge George H. King to finally be in the public domain! This welcome news seems to come at the right …

 Aldec Design and Verification  by Krzysztof Szczur
Krzysztof Szczur
Emulation: Thinking outside of the Big Box
  Independent FPGA Consultant, Doug Amos, has been working in programmable logic and FPGA for over 30 years. He did his first programmable logic design in the mid-80’s (around the time Aldec was born), and since then has designed or supported …

 Embedded Software  by Colin Walls
Colin Walls
Electronics for the sick
I have always for medical electronics interesting. Part of the reason for my interest stems from an occasional feeling that so much of the electronics around me is ultimately pointless. Many Mentor Embedded customers are making consumer devices, …

 Verification Futures  by Mike Bartley
Mike Bartley
DVCon India expected to welcome over 600 delegates
The second DVCon India Conference is expecting to welcome over 600 delegates , up from 450 last year for the first conference. It is running in Bangalore on September 10th and 11th. But why should you be there too? 39 technical papers and 15 …

 Core Values  by Neil Parris
Neil Parris
7 things I learned at 52DAC
Last week I attended the Design Automation Conference as an intrepid reporter to put my ear to the ground and take note of what is happening in the industry. I wrote some daily review blogs of my time on the show floor (which can be seen here, Day …

 Memory Pill  by Bruce Kleinman
Bruce Kleinman
IoT Security Cannot Afford To Be an Oxymoron
Bruce Kleinman Principal FSVadvisors Securing the Internet of Things (IoT) presents opportunities and challenges. IoT security has seen far more press coverage, to date, than actual delivered solutions. The dearth of secure …

 Guest Blogger  by Anne Cirkel
Anne Cirkel
Why the DAC Designer Track is the best deal in town
Memorial Day has come and gone, which means two things: summer is here and DAC is officially upon us. In just over a week the doors will open at Moscone Center with a blockbuster designer keynote: Brian Otis, director of Google’s smart contact …

 What's PR got to do with it?  by Ed Lee
Ed Lee
Design rules built on quicksand?
  Sage CEO Coby Zelnik recently talked with us about how design rules need a formal methodology to account for all the permutations of each rule for today’s and the next generation’s chip designs. What I found alarming was that he …

 Disrupted Hard  by Matthieu Wipliez
Matthieu Wipliez
Numbers don’t lie: there is virtually no interest in high level synthesis
I finally read enough articles about high level synthesis (HLS) that give a sense of hype that just didn't seem to be matched by what I've heard. Now hype is pretty subjective, but numbers are not. For example, the High Level Synthesis group on …

 ExcelliBlog  by Rick Eram, Sales & Marketing VP
Rick Eram, Sales & Marketing VP
Value of timing constraints files beyond STA
Timing Constraint files are one of the best timing and clock data containers available to the designers, yet they are under utilized today and their value is not fully exploited in the design flow. The timing information captured in timing …

 The Instigater: Services with a Smile  by Arman Poghosyan
Arman Poghosyan
EDA Application Porting Guide: Part 1
Introduction With this article we would like to start a series of tutorials covering the migration of EDA applications from Windows to Mac OS X and GNU/Linux. For that purpose we will review the technologies for building user-interface, data layer …

 The Dominion of Design  by Sanjay Gangal
Sanjay Gangal
Asymptotic or Divergent: Three Verification Managers Look to the Future at DAC
What would the Design Automation Conference (DAC) be without a verification panel or two? This year, one in particular takes a look at a variety of verification technologies. Titled, “The Asymptote of Verification,” it will be moderated by Bryon …

 ASIC with Ankit  by Ankit Gopani
Ankit Gopani
Class – The Classic Feature – Part II
Dear AWA Readers Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test …

 NOT EDA  by Sanjay Gangal
Sanjay Gangal
Satya Nadella Named Microsoft CEO
Article source: Microsoft Corp. & Wikipedia Microsoft Corp. today announced that its Board of Directors has appointed Satya Nadella as Chief Executive Officer and member of the Board of Directors effective immediately. Nadella previously …

 Analog Insights  by Hélène Thibiéroz
Hélène Thibiéroz
Optimized Synopsys-MathWorks solution for System-Level Verification
Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, …

 It's Verific !  by Michiel Ligthart
Michiel Ligthart
The demise of VHDL has been greatly exaggerated
I don’t recall when it was the first time that I heard VHDL was a dying language, but for sure it was many years ago, maybe as far back as the late 1990s. Obviously the EDA futurists of then got it very wrong, and I was recently wondering if I …

 AWR Insights  by Sherry Hess
Sherry Hess
AWR: Redefining Design
When I first learned of NI’s Redefining campaign, I thought… yes, makes perfect sense and fits AWR extremely well. Our company was founded almost 20 years ago on the very idea of redefining design for microwave/RF engineers. We began this …

 Dispatches from Boston  by Nanette Collins
Nanette Collins
OneSpin Reaches for the Cloud
As the 50th Design Automation Conference opens, attendees rushing through the doors early Monday may have their heads in a Cloud. Cloud computing that is, and heading straight toward Booth #846. That’s because OneSpin Solutions in Booth #846 …

 Verification is No Simulation  by Dave Rich
Dave Rich
Get your IEEE 1800-2012 SystemVerilog LRM at no charge
At this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge …

 Industry Commentary  by Dr. Russ Henke
Dr. Russ Henke
The EDA and MCAD/MCAE Almanac – Nominal Q3 2012 Part B: MCAD/MCAE Industry
Dear faithful blog reader: Please take a few minutes of your valuable time to read the January 31, 2013 article, “The EDA and MCAD/MCAE Almanac - Nominal Q3 2012 Part B: MCAD/MCAE Industry” You may reach the new January 31 Commentary by …

 IEEE CEDA Corner  by Joel Phillips
Joel Phillips
Alberto Sangiovanni-Vincentelli Celebrates ICCAD’s 30th Anniversary with Look Back at EDA
CEDA turned to Alberto Sangiovanni-Vincentelli of the University of California, Berkeley, to help us celebrate the 30 anniversary of the International Conference in Computer-Aided Design (ICCAD). And, he didn’t disappoint. In a rousing talk …

 EDA Thoughts  by Daniel Payne
Daniel Payne
DAC 2011 Trip Reports – Mostly Transistor Level Tools
2011 was the year of the foundry (TSMC, Globalfoundries, Samsung) at DAC in San Diego. The foundries had bigger booths, bigger events, were on more panel sessions, and had more marketing influence than any other year that I can remember. The …

 Global Business in EDA  by Mo Casas
Mo Casas
Are you missing the opportunity to go global? These tips will signal if you are ready
Expanding business overseas is important. If you are a small EDA vendor, going global before you are ready can be suicidal. Here are some signals that can help you decide you if you are ready to go global. Have you been successful at …

 Become Your Customers  by Saranyan Vigraham

 Open Electrons  by Chitlesh Goorah (Free Electronic Lab)
Chitlesh Goorah (Free Electronic Lab)
Milkymist: pushing further the limits of electronics openness
Everyone has heard of open source software, but can the same principles be applied to hardware? Some people argue that hardware is so expensive to manufacture and modify that it prevents hobbyists from contributing, and thus stifles …

 Stan on Standards  by Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski, Group Director of Standards, Cadence
Japan & SystemC
With all of the excitement in the “front end” of the SOC design/verification/modeling community about Accellera’s UVM, it is easy to loose track of work being done around another significant front end language—SystemC.  For those not aware, …

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