Posts Tagged ‘Verific Design Automation’
Thursday, March 2nd, 2017
DVCon generates a lot of respect, and for good reason. Engineers have attended this conference for over 25 years to further refine their skills in the area of design and verification. Yet, there’s a problem in paradise.
In an industry like EDA that’s super dominated by just three players, there’s little if any room in the industry – or at a conference like DVCon – to showcase the ideas and innovations of the Small Guys. The Big Guys teach tutorials and present papers; the Small Guys get to hang posters in the hallways.
All of that was supposed to change tonight thanks to the sponsorship of the ESD Alliance and OneSpin Solutions, as well as Vista Ventures’ Jim Hogan.
Tonight, six of the Small Guys in verification appeared on a panel moderated by Hogan hoping to get their 60-minute shot at fame. A post-Happy-Hour hour in which to lay out their case for customers to come and sample the kind of innovation that everyone knows is the watchword of technology startups, particularly in EDA.
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Tags: Adnan Hamid, Andy Stein, Avery Design Systems, Breker Verification Systems, Charles Darwin, DVCon 2017, ESD Alliance, Jim Hogan, Montana Design, OneSpin Solutions, Phil Moorby, Prakash Narain, Raik Brinkmann, Real Intent, Rick Carlson, Steve Alvin, Verific Design Automation
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Thursday, June 23rd, 2016
Michiel Ligthart, President and COO of Verific Design Automation, and Rick Carlson, VP of Worldwide Sales, have a proposal for young companies in the EDA industry and adjacent technologies: Come to Verific if your organization is early stage, in need of encouragement and wise counsel, and could benefit from access to Verific software to help you progress towards a commercial product launch.
In a recent phone call, Ligthart and Carlson explained the specifics of the Verific program, and delineated what it’s not: “We are not funding startups,” Ligthart said, “but we have changed our business model over the lifetime of our company to encourage innovation.
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Tags: Austemper, Cadence, Innergy Systems, Joe Costello, Mentor Graphics, NextOp, Oasys, Paul van Besouw, Rick Carlson, Sanjiv Kaul, Synopsys, Tortuga Logic, Verific Design Automation
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Thursday, February 21st, 2013
If you’re in EDA and haven’t heard of Verific Design Automation, it would appear you haven’t been listening. Michiel Ligthart, Verific President and COO, told me in a recent phone call that few people in the industry are unaware of his company’s offerings: “We’re very well known in the industry. Everybody who works in EDA knows us, or if they don’t, we are no more than 2 or 3 phone calls away.
“Verific is a little bit different kind of company. We are a small solutions providers, but we do not have an end-user product. Instead, we provide SystemVerilog and VHDL parsers that we license to EDA companies, and to semiconductor companies that build EDA products for internal use or for their customers.”
I asked why such companies don’t build their own parsers, and he said, “In fact, they could. These are based on IEEE standards and anyone could build them, but the parsers must be the same for everyone. If you can buy them from somebody else, rather than build them, it means you can concentrate on your distinctive solutions. Verilog parsers from companies like Cadence or Synopsys all have to adhere to the same standard.”
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Tags: Abhijit Chakrabarty, Michiel Ligthart, parsers, Rob Dekker, SystemVerilog, Verific Design Automation, VHDL
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