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Posts Tagged ‘GlobalFoundries’

pre-DAC 2013: TSMC certifies ATopTech, CDNS, MENT, SNPS

Thursday, May 30th, 2013

 

In the old days, TSMC made a big toolflow announcement every year at DAC, and hosted a lively ‘partner pavilion’ where dozens of companies were showcased in small auxiliary booths that stood in addition to their conventional booths elsewhere in the Exhibit Hall.

At DAC 2103 in Austin, however, something different is happening. Hosted by GlobalFoundries, this year’s ‘foundry pavilion’ will showcase countries, not corporations: “The DAC Global Forum celebrates contributions and future plans of nations around the globe to the field of electronic design in past (sic) 50 years.” Should be very interesting; check out Booth #137 in Austin.

In the meanwhile, TSMC’s taking this week prior to DAC 2013 to announce various tool certifications, including FinFET v0.1 design enablement: “The tool certification serves as the foundation of design infrastructure for 16-nanometer FinFET technology.”

It’s always fun to read through these types of joint announcements, at least if you’re easily amused by the exercise of comparing the quotes embedded in dueling Press Releases. TSMC Senior Director Suk Lee, for instance, is quoted in all four press releases paraphrased below, sent out this week from ATopTech, Cadence, Mentor, and Synopsys.

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DAC 2013: Innovation Square

Thursday, March 21st, 2013

 

It’s time to start exploring what’s coming up at DAC 2013 in Austin the first week in June, and one way to do that is to visit the conference website. There you’ll find a variety of interesting things including an interactive Exhibit Hall map, which allows you to run your mouse over any booth and see which company’s going to be located there. Maybe that feature’s been available in years past, but it’s still pretty cool.

Something that certainly is new this year at DAC, however, is Innovation Square. I’ve boldly cut-and-pasted the graphic from the DAC website into this blog so you can see what it entails, which is this: You pay the DAC organization $5500 and for that you get a kiosk-like space, a 24-inch computer monitor, an electrical hook-up for your other stuff, booth-unit graphics, a shared private meeting suite with a schedule that you’ll know in advance, and one paid-in-full conference registration.

In other words, you get a “turn key package” that allows you to have a foot on the ground at DAC without enduring the mystery of “What’s this all going to actually cost me?” True, it looks like any particular company in Innovation Square only has about 15 or 20 square feet of show floor, but if otherwise you couldn’t afford to be on the show floor at all in Austin, this is a great innovation indeed.

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GSS: a spirited defense of FDSOI

Thursday, December 13th, 2012

 

When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.

Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.

We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”

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DATE: Design, Automation, Test & Embedded

Saturday, March 3rd, 2012

The premier EDA conference in Europe – many say, in the world – will be in Dresden this year, starting March 12th. There’s a certain something about DATE, a unique quality and consistent energy that runs throughout this conference that really sets it apart, whether in Nice, Munich, Grenoble, or Dresden.

Now in its 15th edition, Design, Automation & Test in Europe seems to get better with each passing year – more refined, focused, and confident, and more unabashedly academic, while still offering a rich experience for exhibitors wanting to showcase their latest and greatest.

With 55+ exhibitors this year, over 200 papers selected from almost a thousand submissions for the 2012 conference, 77 different technical sessions, keynotes from Bosch Automotive Electronics Division President Klaus Meder, and GlobalFoundries Senior Vice President for Design Enablement Mojy Chian, a host of tutorials, panel discussions, and workshops, a Sigda-sponsored PhD forum, and the annual EDAA Lifetime Achievement Award presentation – this year going to UC Berkeley’s own Prof. Alberto Sangiovanni-Vincentelli – DATE is on tap to deliver another terrific week-long event.

University of Tübingen Dean of Science Prof. Wolfgang Rosenstiel is General Chair for DATE 2012. Not surprisingly, when we spoke by phone on March 2nd, he was extremely enthused about the Dresden event. I asked him how the conference has evolved over the years.

Dr. Rosenstiel said, “DATE started in 1998 as the merger of two other European conferences, EURO-DAC and ED&T. Since then, DATE has taken place every year, mainly between France and Germany.

“What has changed over the years? While we have kept the central theme of design, automation, and test in Europe, from there we have widened the focus in two directions.

“The applications of microelectronics have come more clearly into focus at DATE, with special tracks which continue to grow, and there has been an increasing emphasis on embedded systems.

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