Posts Tagged ‘formal verification’
Tuesday, August 22nd, 2017
In a recent conversation with OneSpin’s Dave Kelf, he laughed when I asked him to characterize the complexities of meeting functional safety standards when developing automotive electronics. “It’s a whole rat’s nest of certification,” he said, “and as an industry we’re not there yet.
“However, at OneSpin we have a good handle now on what you need to do to make these cars safe. We’ve been working for quite a while with Bosch, Infineon, and other companies that really have a good idea of what needs to happen with the chips in cars to make them safe.
“In fact, a large part of the regulations come from these guys because they’re the experts, along with some level of government oversight, in trying to make sense of it all.”
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Tags: Bosch, Dave Kelf, formal verification, Hamming code, Infineon, ISO 26262, OneSpin
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Thursday, November 5th, 2015
Since initiating their Decoding Formal Club in October 2013, Oski Technology has hosted this much-needed get-together every quarter, most recently on October 21st of this year at the Computer History Museum in Mountain View. I was fortunate to attend the debut meeting in 2013, so it was interesting to hear from Oski VP Jin Zhang that the support group is proving valuable to the growing numbers who attend.
“The first time we held the meeting,” Zhang said, “it was by invitation only, and we included about a dozen folks. Since that first event, we have continued to use the same room at the Computer History Museum, a room that can hold up to 40 people.
“The workshop, however, is continuing to grow very nicely, so we are faced with either finding a new venue or working with the museum to arrange for a bigger room for our next meeting in the first quarter of 2016.”
Zhang said interest in the event has increased to the point that people sign up to attend as soon as the date and time are announced. “They want to be sure they’ve got a spot,” she said.
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Tags: Apple, ARM, Broadcom, Cadence, Decoding Formal Club, formal verification, Google, Intel, Jin Zhang, Mentor Graphics, NVIDIA, Oski Technology, Synopsys
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Monday, April 21st, 2014
In the moments prior to Cadence’s quarterly earnings call this afternoon, the company released news of the acquisition of Jasper Design Automation for $170 million, less $24 million in cash, and a small tremor rippled out across the EDA Nation.
Paraphrasing Cadence CEO Lip-Bu Tan in the early minutes of his 5pm ET earnings call: We are very pleased to announce a definitive agreement to acquire Jasper Design Automation. This will help us to further meet our customers’ needs for more advanced verification solutions, particularly today as verification now represents 70% of the cost of SoC development. Together, Cadence and Jasper can move forward, offering the strong formal verification solutions leading customers need. In addition, Cadence is also very pleased to be bringing on board the strong team at Jasper, a team with excellent real-world experience.
All good stuff, yes? So why any tremors in our beloved little EDA Nation?
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Tags: Aart de Geus, BDA, Cadence, Coverity, EDAC, formal verification, Forte, Innovation, Jasper Design Automation, Kathryn Kranen, Lip-bu Tan, M&A in EDA, Mentor Graphics, Oasys, Synopsys, Wally Rhines
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Thursday, March 6th, 2014
Oh my gosh: If you arrived at DVCon 2014 at 10:45 am on Tuesday this week, you’d have wondered if you’d wandered into the wrong conference. What happened to sedate, dignified DVCon? Standing at the registration desk on the first floor of the DoubleTree Hotel in San Jose, the volume of noise and conviviality sweeping down the staircase from the upstairs mezzanine was unprecedented. What was going on up there? The DVCon morning poster session, awash in company reps and their ideas, and engineers anxious to engage with both.
When I got to the top of the staircase, I took a moment before plunging into the crowd, amazed at the vitality and the numbers of people hobnobbing among the posters. It wasn’t surprising to learn later in the day from DVCon General Chair Stan Krolikoski that over a thousand people – attendees and exhibitors combined – were at this year’s conference. Clearly, DVCon is enjoying an extraordinary renaissance, so much so that DVCon Europe will be debuting this October in Munich, with DVCon India, DVCon China, and DVCon Japan now in the planning stages. Like I said, omg.
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Tags: Andreas Meyer, ARM, DVCon 2014, DVCon Europe, formal verification, Jim Hogan, Mentor Graphics, Oracle Labs, Ram Narayan, Rich Edelman, Stan Krolikoski, TI, Vaibhar Mahimkar
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Wednesday, September 12th, 2012
This is a great story: Oski Technology decided to prove the validity and efficiency of Formal Verification, and proposed a public challenge for themselves at DAC – a 72-hour window of time in San Francisco whereby they would attack a design problem never before seen, analyze it, propose a verification plan, and execute on that plan between 5 pm on DAC Sunday and 5 pm on DAC Wednesday.
To get a design problem, Oski Technology put out a request for proposal to different companies. The design could be at any stage in development, but had to include the RTL and some level of specifications for what the architecture should do, as well as some simulations.
Among the 5 respondents, Nvidia’s suggested problem was the most appropriate: It was a design that was still not complete and needed verification. More importantly, Nvidia was not afraid to have possible bugs or flaws in the design made public, a sign of their own confidence. So at 5 pm on Sunday, June 3rd, the Oski Technology team opened the files provided by Nvidia.
I’ll let Vigyan Singhal, Oski Technology’s President and CEO, take the story from there in his own words. Vigyan and I spoke by phone on September 12th, the same day a 6-minute video of the whole process was made available by the company. [Here’s the link on YouTube.]
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The challenge …
 Per Vigyan Singhal: “We had gotten the design in advance from the verification manager at Nvidia, but couldn’t even look at the documentation until 5 pm on Sunday, let alone the RTL files. Then after we opened everything, we looked at the code and the design specifications and went from there.
“Initially during the first night and the next morning, we were mostly doing planning. As we learned more about the design, as is usual with this type of thing, we found some unexpected things. Some of the sub-modules were missing from the design. Nvidia had given us the simulation waves, however, so we could guess the functionality and from there wrote Verilog for those little modules.
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Tags: 72-hour Verification Challenge, DAC 2012, formal verification, NVIDIA, Oski Technology, Vigyan Singhal
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Wednesday, July 11th, 2012
The concept of a Grand Challenge is an established one in engineering, so here in 2012 what are the Grand Challenges in EDA? Let’s go out on a limb and name a few candidates:
No.1) Low power: This is the critical problem here in the era of mobile everything. If you can’t guarantee low power for your device, it’s going to go dark way too soon and be way too hot in the meanwhile. Great challenges remain in perfecting the tools to make this all happen.
No.2) Formal verification: There just has to be a way to guarantee that what we meant to design, has been designed and then manufactured. Isn’t that the goal of formal verification, and isn’t it true that we’re not quite there yet?
No.3) 3D-ICs: In the last several years, this one’s gotten a lot of attention, but it appears that there’s still a lot of work to do – at least on the logic side of the equation. Clearly more tools are needed.
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Tags: 3D-ICs, co-design, EDA, formal verification, Grand Challenge, hardware/software co-design, low power, reconfigurable hardware, system-level tools
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