Archive for October, 2017
Thursday, October 26th, 2017
Dr. Philippe Faes and Dr. Hendrick Eeckhaut together founded Sigasi in 2008. Since that time, Belgium-based Sigasi has accomplished the impossible: Taking the best elements of software design and applying them to hardware design. The Sigasi Studio IDE takes the type of feature-rich development environment that facilitates software design and redefines it for hardware design.
Early one morning last week, I spoke by phone with Hendrick Eekhaut, who serves as CTO at Sigasi. He was in Belgium, I was in California. After our conversation, he headed out to dinner; I headed in for breakfast.
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Tags: DAC, DVCon, Eclipse, EDA, Emacs, ESD Alliance, Ghent, Hardware design, Hendrik Eeckhaut, Philippe Faes, Sigasi, Sigasi Studio, SystemVerilog, Verilog, VHDL
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Thursday, October 19th, 2017
Copenhagen-based Teklatech is such an interesting example of an EDA company: similar in many ways to other organizations in the ecosystem, but highly unusual as it is based in Denmark. When Founder & CEO Tobias Bjerregaard and I spoke by phone this month, he began with the motivation for his company’s technology.
The discussion then moved to the business challenges within EDA, a topic that Bjerregaard said he always enjoys discussing. As he feels that Teklatech is providing critical solutions for today’s semiconductor designs, it’s not surprising that his enthusiasm here is palpable, for the industry and the trends that drive it.
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Tags: Ansys, FloorDirector, power integrity, RedHawk, Teklatech, Tobias Bjerregaard
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Thursday, October 12th, 2017
DVCon Europe 2017 will be in Munich next week, a great destination for tourists and technologists alike. This is the fourth year the conference will occur in Europe, the original Silicon Valley based version now in its 27th year.
DVCon Europe General Chair Oliver Bell and I spoke this week by phone about the upcoming event; he was in Germany and I was in Northern California. I offered that Munich is a beautiful city, and he agreed.
“The conference will be in downtown Munich,” Bell said, “at the Holiday Inn. This is a really nice hotel, located near to Marienplaz, and easily reachable from public transportation.”
Bell then laughed and acknowledged that, as famous as the city’s Oktoberfest may be, it’s better that DVCon is being held several weeks after that particular annual exuberance has run its course. The city’s just that much more calm and enjoyable, he noted, after the hundreds of thousands of Oktoberfest revelers have returned to their normal pursuits.
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Tags: 2017 DVCon Europe, Accellera, ARM, Audi, Berthold Hellenthal, Bosch Sensortec, Cadence, Horst Symanzik, Infineon, Intel, Martin Barnasconi, Mentor Graphics, Munich, Nokia, Oliver Bell, Rohde & Schwarz, STMicro, Synopsys, SystemC Evolution Day, Technical University of Munich, UVM
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Thursday, October 5th, 2017
Taking guidance from their website, Silicon Valley based Helic provides “EDA software that mitigates the risk of electromagnetic crosstalk in high-speed and low-power SOC designs.”
The company’s products include VeloceRF, an inductive device compiler and modeling tool which provides DRC clean devices for geometries as low as 10 nanometers; RaptorX, a pre-LVS electromagnetic modeling tool; and Exalto, a post-LVS RLCk extraction tool that captures unknown crosstalk including electrical, magnetic, and substrate coupling.
In other words, Helic is a company with a very technical portfolio of products, which can be daunting if one wants to speak with the leadership.
But that was not the real problem posed during my recent conversation with Helic President and CEO Yorgos Koutsoyannopoulos. The last time the two of us spoke, he made a bet I could not pronounce his name correctly. I won that bet, although Koutsoyannopoulos then proceeded to pronounce my name correctly as well, something that fewer than 1-in-10 in EDA can actually do.
Alas during our recent conversation – the one documented below – the Helic CEO could still pronounce my last name correctly, but I stumbled over his.
In my defense, Koutsoyannopoulus has 16 letters, 56% of which are vowels, and I hadn’t practiced in advance of our call. My last name only has 8 letters, but 63% of them are vowels, so mine is actually more difficult to pronounce. I should not have let Yorgos best me in this contest. Next time I will be better prepared.
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Tags: Ansys, Bob Smith, electromagnetic crosstalk, ESD Alliance, finFET, Helic, TSMC, Yorgos Koutsoyannopoulus
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