Posts Tagged ‘TrekSoC’
Monday, August 19th, 2013
No SoC verification engineer worthy of the title would argue that coverage is unimportant. Even back in the 1980s, before commercial coverage tools and industry standards were available, leading ASIC teams manually added coverage code into their testbenches. They checked that key state machines visited all legal states or made all legal transitions, or that a processor executed all opcodes in its instruction set, over the course of a simulation test.
Verification teams who ignored coverage in those days were at risk of letting bugs slip through to silicon. The old maxim “if you don’t verify it, it’s broken” summed the situation up well. Today, leading SoC teams have adopted system coverage. Those who are ignoring this aspect of coverage are at risk of letting serious system-level bugs slip through. Let’s talk about system coverage and why it’s different from other metrics in use today.
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Tags: Breker, code coverage, concurrency, coverage, functional coverage, functional verification, graph, scenario model, SoC verification, system coverage, TrekSoC
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Tuesday, July 23rd, 2013
Folks who have been following Breker for a while know that we like the phrase “begin with the end in mind.” It succinctly summarizes why our use of graph-based scenario models is different than traditional constrained-random testbenches.
Suppose that you want to trigger a particular behavior within your design as part of your verification process. With a testbench, you have control over only the design’s inputs, so you might issue a series of input stimulus changes that you believe will cause the desired behavior. You may hit your target, or you may not. Automating your testbench with the constrained-random capabilities of the Universal Verification Methodology (UVM) reduces the manual effort, but there’s still no guarantee that you will trigger your targeted behavior.
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Tags: Breker, constrained-random, EDA, functional verification, graph, scenario model, test generation, TrekSoC, uvm
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Tuesday, July 16th, 2013
As you may have noticed, we call Breker “The SoC Verification Company” because we truly believe that we are defining a new category of EDA tools for SoC verification that has not been adequately addressed by other approaches. In the spirit of an engineer defining his or her terms before use, and with a nod to the long-running TV game show Jeopardy, let’s discuss what defines SoC verification and why it is different from verification of IP blocks and other types of chips.
Let’s start one clue higher on the Jeopardy board, with “SoC” for $400. What exactly is a system on chip (SoC)? Some would argue that any large, complex chip qualifies. We beg to differ. Should a pure processor, no matter how powerful, be called an SoC? Alternatively, should a giant network crossbar switch with no central processor be considered an SoC? The Breker viewpoint says that neither qualifies. We believe that an SoC contains at least one reasonably powerful embedded processor (8-bit MCUs don’t count) and multiple IP blocks interconnected by some sort of bus or fabric.
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Tags: Breker, EDA, functional verification, integration verification, jeopordy, SoC, SoC verification, TrekSoC
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Tuesday, May 7th, 2013
If you follow EDA at all, you’re surely familiar with the Design Automation Conference (DAC). This is the biggest annual show for the industry, combining a world-class technical program with a lively and comprehensive trade show. If any company in EDA does not exhibit at DAC, rumors of serious financial troubles or even imminent death are sure to circulate. Of course Breker is very much alive and very supportive of DAC. We’ve been there for several years now, but this year in Austin June 2-6 will be special for many reasons. Please allow me to explain.
For a start, this is the 50th anniversary of DAC and its predecessor conferences, so there is a big party at Austin City Limits and a number of other special events. This is also Breker’s 10th anniversary, so we’re celebrating at DAC as never before. Furthermore, this is the first time that DAC has ever been held in the high-tech hotspot of Austin, so there will be lots of new things to do and see even for long-time DAC attendees such as me. On top of that, Breker was founded in Austin and was headquartered there until moving to Silicon Valley two years ago. As one of the few EDA companies “born in Austin” we’re excited to return for this big show.
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Tags: Breker, dac, EDA, functional verification, SoC verification, Trek, TrekSoC
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Tuesday, April 9th, 2013
Welcome to the birth of a new blog on EDACafé, “The Breker Trekker” from Breker Verification Systems. The term “Trekker” refers to our main product, TrekSoC, and its underlying Trek engine technology. We also mean to suggest “trek” as in a long journey with some challenges and many rewards along the way, appropriate for a small software company still early in our own journey. If you happen to be a Star Trek fan and identify yourself as a trekker, then by all means please become a fan of Breker, too.
Let me start by introducing myself, Tom Anderson, since I’ll be writing the majority of the blog posts. You can read a brief bio just above; I’ve been in electronic design automation (EDA) marketing for about 10 years after working in applications, CAD management, design management, and ASIC design. I joined Breker early last year (2012) as TrekSoC was poised to go from a product used by a small set of early adopters to a mainstream technology. That journey is underway now and I’m having great fun helping to make it happen.
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Tags: Breker, functional verification, SoC verification, Trek, TrekSoC
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