Posts Tagged ‘Synopsys’
Wednesday, May 28th, 2014
DAC is back, Jack! The big show returns to San Francisco for two years before heading back to Austin. Last year was a special one for Breker, with our 10th anniversary as a company, the 50th year of DAC, and the first time for the show in Austin, our birthplace. But no location draws more visitors and more buzz than San Francisco. It’s a short train ride from traditional Silicon Valley and arguably part of an extended definition of Silicon Valley that includes a fair chunk of the Bay Area.
This year’s show promises plenty of excitement, and we’d like to fill you in. Of course, we will be there as part of the always lively exhibit floor. Those of you who attended DAC in Austin will surely remember our naval-themed “USS Ice Breker” booth, which we loved so much we’re shipping it to San Francisco. No visit to the DAC exhibits would be complete without stopping by to see Breker in booth 2602 and taking a “cruise” with us. You can request a meeting at a specific time by visiting our DAC signup page.
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Tags: austin, Breker, dac, dvcon, EDA, formal analysis, functional verification, graph, IBM, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si, Verdi
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Tuesday, April 22nd, 2014
Yesterday may well go down in EDA history as one of the most important days in the evolution of the market for formal analysis. If you had asked me why yesterday morning, I would have said it was because I was attending the third “Decoding Formal Club” meeting sponsored by formal consulting experts Oski Technology. The range of companies represented there, and the enthusiasm for the topic, was a clear indication that formal has become an A-list technology for many verification teams.
So I planned to write today’s post about this meeting. But then, just as it was ending and Oski was thanking all the participants, news broke that Cadence had acquired formal leader Jasper Design Automation for $170M. Of course, this news was of intense interest to the attendees. It made yesterday “Acquisition Day” for formal analysis, so I’ll dub it “A-Day” and provide some thoughts in this post. I will talk a bit about the meeting as well, but will go into more details about the material presented in a future post.
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Tags: 0-In Design Automation, Breker, Cadence, EDA, equivalence checking, formal analysis, functional verification, jasper, mentor, simulation, SoC verification, Synopsys, Verplex
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Tuesday, April 8th, 2014
Some readers may recall that I was on the panel “Is Software the Missing Piece In Verification?” at this year’s DVCon. I mentioned a bit about it in my summary of that show, and moderator Ed Sperling has done an outstanding job of transcribing the panel discussion and transforming it into one of his signature “Experts at the Table” three part series on SemiconductorEngineering. I encourage you to read all three parts since a bunch of interesting topics came up.
Cadence recently published an odd blog post that appeared to be based on the panel: it showed a photo of the panelists and included quotes from several of them, although it mentioned neither DVCon nor the panel. Perhaps they were trying to make it sound as if they held a separate event. They quoted their own representative, the panelist from Vayavya, and the panelist from Intel (although they didn’t list his affiliation). But they did hit on one of the more lively topics of the panel: the changing role of the verification engineer.
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Tags: Breker, Cadence, dvcon, embedded programming, functional verification, hybrid, Intel, SoC verification, software-driven verification, Synopsys
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Wednesday, March 19th, 2014
Perhaps by now you’re tired of reading about DVCon, but our last few posts have drawn very good readership so we know that the show is important to the verification-minded engineers who read The Breker Trekker. Another show, or more accurately a series of shows, has strong verification content and draws well from the verification community. We’re talking about the series of Synopsys Users Group (SNUG) events held worldwide to much acclaim from attendees and participating vendors.
According to the SNUG site, Synopsys has 13 shows scheduled annually in Asia, Europe, and North America, drawing nearly 9000 users. That’s a very impressive series of events by any measure and a sign that the EDA market leader invests heavily in educating its users and providing a forum where they can interact among themselves and with Synopsys technical experts. Next week is the 2014 edition of SNUG Silicon Valley, and we want you to know that Breker will be there.
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Tags: Breker, dvcon, functional verification, SNUG, SoC verification, Synopsys, TrekSoC, TrekSoC-Si, verification IP, VIP
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Tuesday, February 25th, 2014
Next week (March 3-6) marks the return of the most important annual event for verification engineers: the Design & Verification Conference & Exhibition 2014, better known as DVCon. Its home remains the DoubleTree hotel in San Jose, a Silicon Valley landmark and site of many interesting conferences going back to its original days as the Red Lion Inn. Breker will be there in force, so we’d like to tell you about our activities as well as preview the technical program.
Of course, Breker will be participating in the exhibition portion of the show. This has expanded from previous years. The exhibit floor will be open on Tuesday (March 4) and Wednesday (March 5) from 2:30pm to 6:00pm as usual. However, a special preview on Monday from 5:00pm to 7:00pm has been added this year. You’ll have plenty of time to stop by to visit Breker in booth number 902 and (if you must) perhaps some other vendors as well.
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Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, panels, scenario model, simulation, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si
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Tuesday, December 10th, 2013
As you likely know by now, Breker’s primary focus is on verifying SoCs with one or more embedded processors. Sometimes these processors are homogenous, most commonly either the Intel/AMD x86 or ARM architecture. Other SoCs have multiple heterogeneous processors, possibly a diverse mix of cores from x86, ARM, MIPS, ARC, Tensilica, etc.
The trade press devotes a lot of virtual ink to covering the “war” for embedded processor dominance. An article last week made the case for ARM winning. A recent white paper discussed “heterogeneous multi-processing” using ARM’s “big.LITTLE” approach of multiple cores with the same architecture but different performance characteristics. Another article reminded us not to forget about DSPs in the heterogeneous mix. The same could be written about GPUs. So what is Breker’s take on all this?
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Tags: AMD, ARC, ARM, Breker, DSP, EDA, functional verification, GPUs, Intel, IP, Synopsys, Tensilica, verification IP, x86
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Tuesday, November 26th, 2013
The Breker Trekker has been publishing for about seven months now, with 32 posts to date, so running just about once a week. When we started, we committed a new post every two weeks so we’ve been running well ahead of our own expectations. We’re very happy with the growth of our readership and we’d like to take this chance to thank every one of you reading this.
Frankly, we have not been as successful at driving an ongoing dialogue via comments. We’ve had a few comments here and there but not nearly as many as we would like to see. So for this week’s post we’re trying something different: posing a question directly to our readers and heartily encouraging all of you to share your thoughts by leaving a comment at the bottom. Today’s topic: which conferences and trade shows do you find most useful?
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Tags: arrm techcon, Cadence, CDNLive, conference, dac, dvcon, EDA, functional verification, SNUG, Synopsys
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Tuesday, August 27th, 2013
From the blog stats it seems clear that late August is a slow time with lots of folks on vacation, so I’ll take a break from the heavy technical topics to chat about the industry. Long before I worked for an EDA company, I was an active participant as a user of EDA tools and as a CAD manager tasked with evaluating them and integrating them together. In that role, I loved working with interesting startups that had new ideas for electronic development.
It was part of my job to follow the EDA industry closely so that we could choose our tool investments based on both strength of technology and likelihood of vendor success. It seemed to me that the industry was divided into only three categories: major leaguers, minor leaguers, and startups. I observed that nearly all EDA startups disappeared after three or four years, with three possible endgames: acquisition, initial public offering (IPO), or bankruptcy.
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Tags: avant, behemoth, Breker, Cadence, corner store, EDA, functional verification, jasper, major leaguer, mentor, minor leaguer, SoC verification, startup, Synopsys
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Monday, August 5th, 2013
Back in March I published an opinion piece in Chip Design magazine about redefining “DAC” from “Design Automation Conference” to “Development Automation Conference” and “EDA” from “Electronic Design Automation” to “Electronic Development Automation” to reflect reality. It generated a few comments and got a few people talking but that’s as far as it went.
I certainly didn’t expect a groundswell of support or an overnight change, but I was serious about my reasoning. I think that describing the incredibly complex development process for electronic products as “design” is outdated and not representative of the wide range of skills required.
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Tags: Breker, Cadence, CDNLive, dac, dvcon, EDA, EDAC, functional verification, SNUG, Synopsys
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