Posts Tagged ‘SNUG’
Thursday, March 26th, 2015
As we discussed in last week’s post, the past two days we were busy with activities at SNUG Silicon Valley, the annual focus for all things Synopsys. On Monday we exhibited in the Designer Community Expo, which drew programmers, architects, and verification engineers in addition to hardware designers. We have always been impressed by the verification teams we meet at SNUG. They’re all working on hard projects and open to new ideas that will help them find more bugs more quickly.
We also had the pleasure of speaking for the first time in the SNUG technical program, with a talk on “Integration of Portable Test Cases and System-Level Coverage with Verdi HW SW Debug Using VC Apps” in the VC Apps Developer Forum session yesterday. We had a nice response from the 65 or so attendees and were delighted with their interest. Since the talks in this session do not have corresponding papers in the SNUG Proceedings, we’d like to use today’s post to fill in the technical details.
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Tags: Accellera, Breker, DCE, debug, design IP, EDA, functional verification, graph, graph-based, HW SW, portable stimulus, Santa Clara, scenario model, simulation, SNUG, SoC verification, test generation, Universal Verification Methodology, uvm, VC Apps, VCS, Verdi, verification IP, VIP
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Wednesday, March 18th, 2015
Following a very successful DVCon in San Jose two weeks ago, next week we travel a few miles up the road to the Santa Clara Convention Center for the Synopsys Users Group (SNUG) Silicon Valley event. This will be our third year in a row exhibiting at this show, and it has become one of our favorites. We will also be speaking for the first time ever, and we’ll fill in all the details shortly. But let’s start by looking at why this show stands out and why we enjoy it so much.
SNUG actually has quite an interesting history. It began in 1991 as a way for Synopsys users to discuss common problems and solutions, meet with technical experts from the company’s R&D and AE teams, and learn about new products and features. Unlike many single-vendor conferences, SNUG has been driven largely by the users. They choose the papers to be presented and make many of the key decisions on how the event is run. Synopsys of course provides support in many ways.
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Tags: Accellera, Breker, DCE, debug, design IP, EDA, functional verification, graph, graph-based, HW SW, portable stimulus, Santa Clara, scenario model, simulation, SNUG, SoC verification, test generation, Universal Verification Methodology, uvm, VC Apps, VCS, Verdi, verification IP, VIP
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Wednesday, February 18th, 2015
In any industry dominated by a few large companies, it is important for the smaller players to ensure that their products work well with the broader solutions from the majors. Recognizing this need, and sometimes encouraged by legal action, the large companies develop partnership programs to enable and even foster integration with their solutions. All this is true for the EDA business, where the “Big 3” work closely with many smaller vendors for the sake of their mutual customers.
In Breker’s case, we generate SoC test cases that run on a variety of software and hardware platforms. We do not build any of those platforms ourselves but we need to verify that our test cases can run properly on them. Accordingly, we are members of several important partnership programs and we work closely with other vendors to find and fix any interoperability issues before our customers run into them. In this week’s post, we focus on how we work with Synopsys, the EDA market leader.
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Tags: Accellera, Breker, debug, design IP, EDA, functional verification, graph, graph-based, HW SW, portable stimulus, scenario model, simulation, SNUG, SoC verification, test generation, Universal Verification Methodology, uvm, VC Apps, VCS, Verdi, verification IP, VIP
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Tuesday, September 9th, 2014
What verification engineer doesn’t love the occasional conference? It’s a chance to get out of the cubicle farm, hang out with colleagues from other companies, listen to stimulating technical talks, and catch up on what EDA, IP, and semiconductor vendors have been doing. Even in a time of tight travel budgets, the right conference can provide dividends far beyond its cost. There are a lot of smart people in the electronics industry and it’s valuable to share problems and solutions with them.
There are actually quite a few conferences and trade shows that have interesting verification content and draw significant numbers of verification engineers. One of the most-read posts in the history of The Breker Trekker blog was a discussion on which conferences verification engineers like best. We are constantly evaluating which events provide the most value to us and our customers, and find ourselves in the unusual position of having four shows scheduled in four locations over the next four weeks.
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Tags: Accellera, apps, ARM, austin, Bangalore, Boston, Breker, Cadence, coherency, CVC, DV, dvcon, ESL, functional verification, India, mentor, Newton, portable stimulus, Santa Clara, SNUG, Synopsys, TechCon, TrekSoC, TrekSoC-Si, TrekUVM, uvm
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Tuesday, April 1st, 2014
In our last post, we discussed some details of the demo that we showed at the DVCon and SNUG Silicon Valley events, in which TrekSoC-Si generated a test case, downloaded it into a commercial SoC (a TI OMAP4430 with dual ARM cores), and ran it in the actual chip. Our focus last time was on Breker’s unique visualization for the multi-threaded, multi-processor test cases that we generate. Specifically, we provide the same display for a test case running in silicon as we do for one running in simulation or simulation acceleration.
Even more interesting is our ability to display coverage information for test cases running in silicon. You might think that this is impossible unless we’re building coverage structures into the SoC that you fabricate. Customers have been known to build specific types of coverage metrics into their hardware, for example real-time monitoring of bus bandwidth and SoC performance. But that’s not what we’re doing; we can gather highly accurate system-level overage without changing the design a bit.
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Tags: Breker, dvcon, EDA, emulation, functional verification, goals, graph, paths, reuse, scenario model, silicon, simulation, SNUG, SoC verification, system coverage, TrekSoC, use cases
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Tuesday, March 25th, 2014
As we mentioned in our last few posts regarding the DVCon and SNUG Silicon Valley events, Breker exhibited at both shows with an identical demonstration. We showed our latest product, TrekSoC-Si, generating a test case, downloading it into a commercial SoC (a TI OMAP4430 with dual ARM cores), and running in the actual chip. This demonstrated our ability to support all verification platforms, from ESL and RTL simulation through acceleration, emulation, FPGA prototyping, and silicon.
This demo attracted quite a bit of interest and some good questions at both shows, so we thought we’d devote this blog post to filling in a few of the details. We especially want to stress that we provide exactly the same level of visualization for a multi-threaded, multi-processor test case running deep inside an actual chip as we do when it’s running in simulation or simulation acceleration.
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Tags: Breker, dvcon, EDA, functional verification, graph, OMAP, PandaBoard, scenario model, SNUG, SoC verification, Texas Instruments, TI, TrekSoC-Si, use cases
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Wednesday, March 19th, 2014
Perhaps by now you’re tired of reading about DVCon, but our last few posts have drawn very good readership so we know that the show is important to the verification-minded engineers who read The Breker Trekker. Another show, or more accurately a series of shows, has strong verification content and draws well from the verification community. We’re talking about the series of Synopsys Users Group (SNUG) events held worldwide to much acclaim from attendees and participating vendors.
According to the SNUG site, Synopsys has 13 shows scheduled annually in Asia, Europe, and North America, drawing nearly 9000 users. That’s a very impressive series of events by any measure and a sign that the EDA market leader invests heavily in educating its users and providing a forum where they can interact among themselves and with Synopsys technical experts. Next week is the 2014 edition of SNUG Silicon Valley, and we want you to know that Breker will be there.
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Tags: Breker, dvcon, functional verification, SNUG, SoC verification, Synopsys, TrekSoC, TrekSoC-Si, verification IP, VIP
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Tuesday, November 26th, 2013
The Breker Trekker has been publishing for about seven months now, with 32 posts to date, so running just about once a week. When we started, we committed a new post every two weeks so we’ve been running well ahead of our own expectations. We’re very happy with the growth of our readership and we’d like to take this chance to thank every one of you reading this.
Frankly, we have not been as successful at driving an ongoing dialogue via comments. We’ve had a few comments here and there but not nearly as many as we would like to see. So for this week’s post we’re trying something different: posing a question directly to our readers and heartily encouraging all of you to share your thoughts by leaving a comment at the bottom. Today’s topic: which conferences and trade shows do you find most useful?
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Tags: arrm techcon, Cadence, CDNLive, conference, dac, dvcon, EDA, functional verification, SNUG, Synopsys
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Monday, August 5th, 2013
Back in March I published an opinion piece in Chip Design magazine about redefining “DAC” from “Design Automation Conference” to “Development Automation Conference” and “EDA” from “Electronic Design Automation” to “Electronic Development Automation” to reflect reality. It generated a few comments and got a few people talking but that’s as far as it went.
I certainly didn’t expect a groundswell of support or an overnight change, but I was serious about my reasoning. I think that describing the incredibly complex development process for electronic products as “design” is outdated and not representative of the wide range of skills required.
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Tags: Breker, Cadence, CDNLive, dac, dvcon, EDA, EDAC, functional verification, SNUG, Synopsys
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