Posts Tagged ‘graph’
Thursday, June 5th, 2014
The 51st Design Automation Conference (DAC) has passed into the history books with three days of exhibits and a wide range of enveloping technical sessions and tutorials. After returning home, I’m thinking back over the week fondly as I nurse feet that ache more than I thought possible. Before I get back into the usual work routine, I want to capture some of the impressions and thoughts running through my head.
There is no doubt that big forces in the industry are aligning toward our view of SoC verification with graph-based scenario models. Many of the people who stopped by our “USS Ice Breker” booth completely understood that they risked hitting an iceberg with their minimal full-chip verification efforts. Some had heard about Breker from colleagues or had seen us listed in Gary Smith’s and John Cooley’s DAC “must see” lists. Others knew little about us but were attracted by our claim as “The SoC Verification Company.” All wanted to know how we can help them.
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Tags: austin, Breker, dac, dvcon, EDA, formal analysis, functional verification, graph, IBM, partnerships, portable stimulus, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si, Verdi
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Wednesday, May 28th, 2014
DAC is back, Jack! The big show returns to San Francisco for two years before heading back to Austin. Last year was a special one for Breker, with our 10th anniversary as a company, the 50th year of DAC, and the first time for the show in Austin, our birthplace. But no location draws more visitors and more buzz than San Francisco. It’s a short train ride from traditional Silicon Valley and arguably part of an extended definition of Silicon Valley that includes a fair chunk of the Bay Area.
This year’s show promises plenty of excitement, and we’d like to fill you in. Of course, we will be there as part of the always lively exhibit floor. Those of you who attended DAC in Austin will surely remember our naval-themed “USS Ice Breker” booth, which we loved so much we’re shipping it to San Francisco. No visit to the DAC exhibits would be complete without stopping by to see Breker in booth 2602 and taking a “cruise” with us. You can request a meeting at a specific time by visiting our DAC signup page.
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Tags: austin, Breker, dac, dvcon, EDA, formal analysis, functional verification, graph, IBM, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si, Verdi
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Tuesday, May 13th, 2014
As regular readers know, Breker’s claim to fame is the automatic generation of multi-threaded, self-verifying test cases that run on multiple heterogeneous processors within an SoC. The source for the generation process is a graph-based scenario model that captures the design intent and verification space. We chose graphs as an enabling technology more than ten years ago for a number of reasons, some of which we’ll discuss in this post.
The catalyst for this discussion is a new effort within the Accellera standards body to form the Portable Stimulus Specification Proposed Working Group (PWG). Basically, Accellera has formed a proposed working group to determine whether a technical working group should be established to start developing a specification for a standard. What does this have to do with graphs, and Breker? We’ll do our best to explain the history and current status.
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Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, mentor, portable stimulus, pwg, reuse, scenario model, SoC verification, standards, test generation, working group
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Tuesday, May 6th, 2014
Last week I used a talk by Vigyan Singhal, CEO of formal consulting experts Oski Technology, as the springboard for a blog post on how to extend verification planning for formal analysis and graph-based SoC verification. This week, I’m using a panel held at that same “Decoding Formal Club” meeting as the starting point for my thoughts on how to establish an effective team to use relatively new verification technologies such as formal and graphs.
The second half of the meeting was a panel on “How to Build a Productive Formal Team” moderated by Harry Foster from Mentor. The participants included a nice mix of users, while Vigyan rounded out the panel with his unique blend of formal tool development and hands-on usage with many customers. Although there wasn’t much controversy per se, it was clear that everyone had different experiences leading to different opinions on how to build a strong formal team.
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Tags: Breker, constraints, decoding formal, formal analysis, functional verification, graph, jasper, oski, scenario model, simulation, SoC verification
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Tuesday, April 29th, 2014
Last week I mentioned that I attended the third “Decoding Formal Club” meeting sponsored by formal consulting experts Oski Technology. I started out to write about this event but was distracted by the big news that Cadence had acquired formal leader Jasper Design Automation for $170M. As the meeting was winding up, a friend from Mentor picked up the news alert and showed it to me. I pulled up the news on my own smartphone and showed it to Vigyan Singhal, CEO of Oski and also the original founder of Jasper.
So I had the pleasure of informing Jasper’s founder that his old company had been acquired. But I don’t want to let that bit of fun or the Jasper news in general to lead us to forget about the Decoding Formal meeting. There were two primary segments: a presentation from Vigyan on verification planning and a panel of expert users on building a formal team. I’ll talk about the presentation today and cover the panel in a future post.
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Tags: Breker, Cadence, constrained-random, constraints, decoding formal, formal analysis, functional verification, graph, jasper, oski, scenario model, SoC verification, UCIS
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Tuesday, April 1st, 2014
In our last post, we discussed some details of the demo that we showed at the DVCon and SNUG Silicon Valley events, in which TrekSoC-Si generated a test case, downloaded it into a commercial SoC (a TI OMAP4430 with dual ARM cores), and ran it in the actual chip. Our focus last time was on Breker’s unique visualization for the multi-threaded, multi-processor test cases that we generate. Specifically, we provide the same display for a test case running in silicon as we do for one running in simulation or simulation acceleration.
Even more interesting is our ability to display coverage information for test cases running in silicon. You might think that this is impossible unless we’re building coverage structures into the SoC that you fabricate. Customers have been known to build specific types of coverage metrics into their hardware, for example real-time monitoring of bus bandwidth and SoC performance. But that’s not what we’re doing; we can gather highly accurate system-level overage without changing the design a bit.
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Tags: Breker, dvcon, EDA, emulation, functional verification, goals, graph, paths, reuse, scenario model, silicon, simulation, SNUG, SoC verification, system coverage, TrekSoC, use cases
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Tuesday, March 25th, 2014
As we mentioned in our last few posts regarding the DVCon and SNUG Silicon Valley events, Breker exhibited at both shows with an identical demonstration. We showed our latest product, TrekSoC-Si, generating a test case, downloading it into a commercial SoC (a TI OMAP4430 with dual ARM cores), and running in the actual chip. This demonstrated our ability to support all verification platforms, from ESL and RTL simulation through acceleration, emulation, FPGA prototyping, and silicon.
This demo attracted quite a bit of interest and some good questions at both shows, so we thought we’d devote this blog post to filling in a few of the details. We especially want to stress that we provide exactly the same level of visualization for a multi-threaded, multi-processor test case running deep inside an actual chip as we do when it’s running in simulation or simulation acceleration.
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Tags: Breker, dvcon, EDA, functional verification, graph, OMAP, PandaBoard, scenario model, SNUG, SoC verification, Texas Instruments, TI, TrekSoC-Si, use cases
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Monday, March 10th, 2014
In our last two posts, we talked about the 2014 edition of the Design & Verification Conference & Exhibition, DVCon, in San Jose. Now that the show is history, lots of bloggers are summarizing their experience. Since I thought that this was an excellent event all around, allow me to join the chorus of voices praising DVCon 2014.
Here at Breker, our biggest effort goes toward the exhibition. Although it’s a relatively small booth and exhibit floor, we do want to put our best foot forward. So we had all-new signage this year updating attendees on our products and their capabilities. We also showed a very different demo from last year, with our TrekSoC-Si product generating a test case, downloading it into a commercial SoC (a TI OMAP4430), and running in the actual chip. We chose to repeat our very popular giveaway from DAC: a combined flashlight and distress whistle that will come in handy if you perform inadequate SoC verification and hit an iceberg.
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Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, reuse, scenario model, simulation, SoC verification, test generation, TrekSoC-Si
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Tuesday, March 4th, 2014
As we write this post, it’s Tuesday evening and the Design & Verification Conference & Exhibition 2014, DVCon, is halfway over. We could be traditional and have a college marching band entertain us and form schematic diagrams on the field as we wait for the show to resume. We could hire some entertainer whose appeal has faded and who’s willing to do half-time shows to try to resurrect his or her career. But instead we’re going to settle for a simple report.
Monday evening featured, for the first time, an early look at the exhibition floor. DVCon reported that the show has a record number of exhibitors this year, and in fact they spilled out of the DoubleTree ballroom into the lobby. In a time when so many conferences are shrinking, the news that DVCon is growing is most welcome.
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Tags: Breker, dvcon, functional verification, graph, graph-based verification, panel, SoC verification, software-drive verification, TrekSoC, TrekSoC-Si
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Tuesday, February 25th, 2014
Next week (March 3-6) marks the return of the most important annual event for verification engineers: the Design & Verification Conference & Exhibition 2014, better known as DVCon. Its home remains the DoubleTree hotel in San Jose, a Silicon Valley landmark and site of many interesting conferences going back to its original days as the Red Lion Inn. Breker will be there in force, so we’d like to tell you about our activities as well as preview the technical program.
Of course, Breker will be participating in the exhibition portion of the show. This has expanded from previous years. The exhibit floor will be open on Tuesday (March 4) and Wednesday (March 5) from 2:30pm to 6:00pm as usual. However, a special preview on Monday from 5:00pm to 7:00pm has been added this year. You’ll have plenty of time to stop by to visit Breker in booth number 902 and (if you must) perhaps some other vendors as well.
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Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, panels, scenario model, simulation, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si
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