Posts Tagged ‘graph’
Tuesday, August 25th, 2015
For the most part, the terms “verification” and “validation” are used interchangeably in the electronics industry. However, there are many who argue that these are distinct activities in the development of SoC s and systems, performed at different times in the schedule and usually by different groups of engineers. We refer to ourselves as “The SoC Verification Company” and this is a deliberate choice we made. So we thought that it would be useful to define the two terms as we see them and talk about the similarities and differences.
This post was inspired by an article from 2010 that our CFO and co-founder Maheen Hamid discovered recently. It opens with the “usual definitions” as follows:
- “Validation: Are we building the right system?”
- “Verification: Are we building the system right?”
This seems like a good place to start the discussion.
(more…)
Tags: Breker, EDA, formal analysis, functional verification, graph, graph-based, portable stimulus, scenario model, simulation, SoC verification, software-driven verification, static analysis, test generator, Universal Verification Methodology, uvm, validation, VIP
5 Comments »
Thursday, August 20th, 2015
Last week we discussed some of the drivers in the electronics industry influencing the program for the upcoming DVCon India, September 10-11 in Bangalore. The Technical Program Committee has completed its arduous task of selecting among many worthy proposals for sessions and has posted a near-final program. Today we’d like to highlight some of the most interesting aspects of the packed two days, focusing on sessions that we believe will be a particular draw for those who follow Breker and SoC verification.
There are four conference-wide keynote speeches, from Atul Bhatia (formerly of nSys), Harry Foster of Mentor, Manoj Gandhi of Synopsys, and Vinay Shenoy of Infineon. They will set the tone for the event by discussing the high-level challenges in designing and verifying leading-age semiconductor devices. Nick Heaton of Cadence will keynote the Design and Verification Track (DV) while Pankaj Singh of Infineon and Dr. Sacha Loitz of Continental will give invited talks in the Electronic System Level (ESL) track.
(more…)
Tags: Accellera, Breker, CVC, dvcon, DVCon India, EDA, functional verification, graph, graph-based, IBM, mentor, portable stimulus, PSWG, scenario model, simulation, SoC verification, software-driven verification, test generator, Universal Verification Methodology, uvm, veriflabs, VIP
No Comments »
Wednesday, August 12th, 2015
Many of our readers may recall that Breker aggressively promoted the inaugural DVCon India last year. We supported the show itself by sponsoring a booth in the exhibition and delivering three conference talks. It turned out, much to our delight, that that hottest topic at the show was portable stimulus. There was a great deal of interest in the newly formed Accellera Portable Stimulus Working Group (PSWG) and how Breker’s products provided a well-tested solution meeting all of the PSWG’s requirements.
The second DVCon India is less than a month away, on September 10-11 at Leela Palace in Bangalore. I have every expectation that portable stimulus will be a major theme again. We’re also very busy promoting the event to ensure its success, especially since I am co-chair of the Promotions Committee. I will be covering the details of the sessions and our own participation in next week’s blog post. For today, I’d like to focus on some of the industry drivers that are influencing the interest of potential attendees and the selection of content for the technical program.
(more…)
Tags: Accellera, Breker, dvcon, DVCon India, EDA, functional verification, graph, graph-based, mentor, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, software-driven verification, test generator, Universal Verification Methodology, use case, uvm, VIP
No Comments »
Wednesday, August 5th, 2015
In last week’s post, we spent quite a bit of time talking about the concept of a (realistic) use case that reflected how actual users will eventually manipulate the design being verified. Our focus was on Breker’s graph-based scenario models and how they can easily and concisely capture such use cases. We did some research on the term “use case” and found that it seems to be more common in software design and verification than in hardware verification. That caused us to think about how we at Breker seem to be living on the hardware-software frontier.
It’s not uncommon for hardware designers and software engineers to borrow ideas from each other. Code coverage, for example, was well established in software before it was adopted for hardware design and verification languages. With the move from gates to RTL, hardware became just another form of code and therefore more amenable to software techniques. This is just one example showing that the boundary between hardware and software is fuzzy and changing over time.
(more…)
Tags: Accellera, Breker, device driver, EDA, functional verification, graph, graph-based, hardware, hardware-dependent software, HdS, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, software, test generator, use case
No Comments »
Thursday, July 30th, 2015
One of the signs that a technological domain is still fairly young is frequently evolving terminology as the pioneers attempt to explain to the mainstream what problem needs to be solved and what solutions can be brought to bear on the problem. Such is the case with SoC verification. At Breker we used to start explaining what we do by talking about graphs, but shifted to “graph-based scenario models” to emphasize that graphs are perfect for expressing scenarios of real-world behavior.
Our friends at Mentor, also strong advocates for graphs, began using the term “software-driven verification” to describe their approach. We rather like this description, but feel that it can only be applied accurately when embedded test code is being generated and when the embedded processors are in charge of the test case. Now our friends at Cadence have been sprinkling the term “use case” throughout their discussions on SoC and system verification. Let’s try to sort out what all this means.
(more…)
Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, graph-based, mentor, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, test generator, Universal Verification Methodology, use case, uvm, VIP
No Comments »
Wednesday, July 15th, 2015
Recent announcements from IBM and others about supporting EDA tools in the cloud have spurred renewed discussion on this topic, including here at The Breker Trekker. As expected, the recent posts have been very popular with our readers. Those of you who have been following this topic for a while may recall that, almost exactly two years ago, EDA vendor OneSpin announced cloud support for their formal tools. We invited their VP of Marketing, Dave Kelf, to fill us in their experiences since then:
Two years ago OneSpin introduced the cloud version of it’s Design Verification (DV) formal-based products. Some commentators pointed at other failed EDA attempts to make the same move, suggesting more of the same. Others hailed the announcement as a bold move whose time had come. So… did it work out and what have we learned? The results are surprising, and suggest trends that make some EDA solutions a natural fit for the cloud, whereas others are questionable.
(more…)
Tags: Accellera, Breker, cache coherency, cloud, cloud computing, EDA, formal, functional verification, graph, graph-based, OneSpin, portable stimulus, scenario model, simulation, SoC verification, use cases, uvm, VIP
1 Comment »
Tuesday, June 30th, 2015
Last week on The Breker Trekker, we discussed the resurgence of interest in EDA tools in the cloud. Like our first post on the topic two year’s ago, last week’s entry was very popular. Clearly this is a topic of interest to both our regular and occasional readers. Two more announcements regarding EDA in the cloud also surfaced during the recent Design Automation Conference (DAC), so it does seem as if there is more effort going toward finding a technically and financially successful industry solution.
Last week we summarized five barriers that have helped prevent cloud-based EDA from achieving mainstream adoption:
- The EDA vendor’s effort to port to a cloud-based platform
- Worries about GUI and interactive responsiveness
- Ability to support users of cloud-based tools
- Lack of an established, proven business model
- Concerns over security of the design and verification data in the cloud
(more…)
Tags: Accellera, Breker, cache coherency, cloud, cloud computing, EDA, functional verification, graph, graph-based, IP, low power, portable stimulus, scenario model, simulation, SoC verification, TrekApp, use cases, uvm, VIP
No Comments »
Wednesday, June 24th, 2015
It has been almost exactly two years since we discussed the possibility of EDA tools in the cloud here on The Breker Trekker. The post was popular then, and it remains so. In fact, of the more than 100 posts we’ve published, our cloud post remains the second most read. This week, the recent news that IBM will make its EDA tools available in the cloud through a partnership with SiCAD brought cloud computing back to the forefront. Let’s discuss what has changed–and what hasn’t–in the past two years.
The idea of users being able to run EDA tools as leased enterprise software on remote machines has been around for years, well before the term “the cloud” was widely used. Synopsys invested a great deal of time and effort into its DesignSphere infrastructure, initially more of a grid application than a cloud solution as we use the term today. But the difference is not very important; the key concepts are the same and they represent a major departure from the time-tested model of customers “owning” EDA tools and running them in-house.
(more…)
Tags: Accellera, Breker, cache coherency, cloud, cloud computing, EDA, functional verification, graph, graph-based, IP, low power, portable stimulus, scenario model, simulation, SoC verification, TrekApp, use cases, uvm, VIP
No Comments »
Wednesday, June 17th, 2015
As we have discussed before, we have followed the lead of other EDA vendors by packaging aspects of our advanced verification technologies into pushbutton applications (apps). The first in this product line, our Cache Coherency TrekApp, has been very popular since its introduction last year. As we have covered in depth, this is due in part to the trend of large chips becoming multiprocessor SoCs with multi-level caches. The sudden escalation of cache coherency verification from the CPU developer to the system integrator created strong demand for our nicely bundled solution.
There are many other trends ongoing and emerging in the SoC industry, and we have a long list of ideas for possible TrekApps to help address the challenges that are arising. We would like your help in prioritizing our development efforts. We have established a survey listing ten TrekApps under consideration. Please simply check off the ones of most interest to you by midnight Pacific time on June 30. All submissions will be entered into a drawing for a $50 Amazon.com gift card.
(more…)
Tags: ARM, Breker, cache coherency, clock domains, EDA, Ethernet, functional verification, graph, graph-based, IP, low power, PCIe, portable stimulus, scenario model, security, simulation, SoC verification, TrekApp, USB, use cases, uvm, VIP
No Comments »
Thursday, June 11th, 2015
Last week we looked forward to the 52nd edition of the annual Design Automation Conference (DAC), held this week at Moscone Center in San Francisco. Today we look back at the past three days and all of the activity at the show. It was a very busy time for Breker as usual, but there were some special aspects this year that we’d like to mention. We also want to thank the many customers, prospects, colleagues, and even competitors who joined us at various times for provocative discussions and plenty of social networking. As always, we invite you to add your comments on DAC and what you thought about the show.
Overall, the exhibition floor seemed lively for most of the time. We frequently had multiple visitors in our booth, asking questions and watching demos. We focused on two aspects of our Trek product line: immediate availability of portable stimulus and pushbutton verification of cache coherency. We saw lots of interest in both topics and it’s hard to say which drew more attention. Our suite was booked for most of the time, with customers receiving updates from Breker and prospects discussing their verification challenges and how we might be able to help them.
(more…)
Tags: Accellera, Altera, Breker, cache coherency, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, TrekApp, uvm, VIP
No Comments »
|
