Posts Tagged ‘functional verification’
Monday, July 29th, 2013
The recent guest post from OneSpin looking back at the Design Automation Conference (DAC) in Austin was very popular, so we’ve invited some more of our friends from the EDA community to share their experiences. This week we hear from Lianfeng Yang, Vice President of Marketing at ProPlus Design Solutions, Inc.:
This year’s DAC proved to be a journey from Nano-scale SPICE modeling to Giga-scale SPICE simulations and a place where attendees could learn the secrets of design for yield (DFY) during a Wednesday afternoon pavilion panel.
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Tags: Breker, BSIMPro, BSIMProPlus, dac, DFY, EDA, functional verification, ProPlus
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Tuesday, July 23rd, 2013
Folks who have been following Breker for a while know that we like the phrase “begin with the end in mind.” It succinctly summarizes why our use of graph-based scenario models is different than traditional constrained-random testbenches.
Suppose that you want to trigger a particular behavior within your design as part of your verification process. With a testbench, you have control over only the design’s inputs, so you might issue a series of input stimulus changes that you believe will cause the desired behavior. You may hit your target, or you may not. Automating your testbench with the constrained-random capabilities of the Universal Verification Methodology (UVM) reduces the manual effort, but there’s still no guarantee that you will trigger your targeted behavior.
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Tags: Breker, constrained-random, EDA, functional verification, graph, scenario model, test generation, TrekSoC, uvm
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Tuesday, July 16th, 2013
As you may have noticed, we call Breker “The SoC Verification Company” because we truly believe that we are defining a new category of EDA tools for SoC verification that has not been adequately addressed by other approaches. In the spirit of an engineer defining his or her terms before use, and with a nod to the long-running TV game show Jeopardy, let’s discuss what defines SoC verification and why it is different from verification of IP blocks and other types of chips.
Let’s start one clue higher on the Jeopardy board, with “SoC” for $400. What exactly is a system on chip (SoC)? Some would argue that any large, complex chip qualifies. We beg to differ. Should a pure processor, no matter how powerful, be called an SoC? Alternatively, should a giant network crossbar switch with no central processor be considered an SoC? The Breker viewpoint says that neither qualifies. We believe that an SoC contains at least one reasonably powerful embedded processor (8-bit MCUs don’t count) and multiple IP blocks interconnected by some sort of bus or fabric.
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Tags: Breker, EDA, functional verification, integration verification, jeopordy, SoC, SoC verification, TrekSoC
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Tuesday, July 9th, 2013
As you have read, Breker had an excellent Design Automation Conference (DAC) this year. Many other EDA vendors were pleased as well. Today, guest blogger Dr. Raik Brinkmann from OneSpin Solutions shares his experience:
After sitting out DAC last year, OneSpin Solutions was back, exhibiting and demonstrating our innovative formal assertion-based verification and formal equivalence checking solutions. Overall, we considered the 50th DAC to be a great success. From what we heard, we weren’t alone in our assessment. The exhibit floor was busy all three days and the technical sessions hopping. In general, most of the exhibitors were happy with attendance and thought DAC was worthwhile. No one knew what to expect, given the Austin location and the general health of the economy and EDA industry.
We’re pleased with the number of leads we collected from DAC and attribute much of it to our pre-DAC marketing and public relations campaign. We started upping our visibility around November last year and went into high gear at DVCon earlier this year. I highly recommend this strategy to all DAC exhibitors for next year.
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Tags: cloud, dac, EDA, equivalence checking, functional verification, integration verification, OneSpin
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Tuesday, July 2nd, 2013
A year or two ago, cloud computing was a hot topic at EDA events and conferences. The industry’s largest player, Synopsys, talked a lot about running their EDA tools in the cloud and claimed a great deal of customer interest in this area. Earlier this year, CEO Aart de Geus was quoted as saying that “Synopsys had made $0 on it.” What happened? Is the idea of EDA in the cloud dead? What are the issues preventing its adoption?
In talking to customers and reading related articles, I’ve heard of several reasons why the cloud is not yet a factor for EDA. One practical issue is that EDA vendors are not sure how to price cloud-based licenses. If the customer motivation to move to the cloud is to more easily handle infrequently used tools or to provide peak capacity for frequently used tools, indeed the wrong pricing model could cost the vendor money. One technical issue is that some EDA tools are interactive and would be painful to use over the Internet.
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Tags: Breker, Cadence, cloud computing, EDA, functional verification, SoC verification
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Friday, June 14th, 2013
I spent my last few posts previewing and reporting on the 50th Design Automation Conference (DAC) in Austin. As I have mentioned, this was the first time that DAC was held in Austin and so a lot of vendors were nervous about that. I know at least a couple of companies who downsized their DAC crews in anticipation of a smaller show. Well, the numbers are in and DAC did fairly well in Austin. Full-conference passes were 1589, down 16% from 2012 in San Francisco. Exhibits-only passes were 2364, down 15%. The number of both staffers was down 26%, reflecting both consolidation in the EDA industry and smaller crews.
No one really expected Austin to match San Francisco, but the numbers are quite respectable. What was especially interesting was that the number of exhibits-only passes exceeded by 15% those in San Diego in 2011. It seems that the local electronics community really turned out at DAC this year, already clear to us exhibitors since we saw many new faces we had not seen at shows in other locations.
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Tags: austin, Breker, dac, EDA, functional verification, SoC verification
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Friday, June 7th, 2013
My last post provided some impressions on the first two days of the first-ever Design Automation Conference (DAC) in Austin. It was very personal and perhaps even a bit self-congratulatory since I was so excited about how well the conference had gone for Breker. Well, this post isn’t going to be any less upbeat since the final day of the show was also great fun. For a start, we scanned more badges on Wednesday than on either Monday or Tuesday. That has to be a DAC first.
In addition to the skit and musical enterta inment in our DAC booth theater, we also offered a brief product overview and several guest presentations. I’d like to thank Brian Bailey of EDA DesignLine and Brian Bailey Consulting, J.U. Nambi of CMR, and Srini Venkataramanan of CVC. Each of their talks drew a crowd and contributed to the diversity of our theater program. I’d like to expand this even further at future shows, with customers and additional partners offering their thoughts.
I was pleased with the technical panel “Disruptive Verification Technologies: Can They Really Make a Difference?” on Wednesday morning. Moderator Brian Bailey wove together several threads about the state of functional verification and a couple of “non-answers” from the panelists opened up some additional topics. I thought that Breker CEO Adnan Hamid did a nice job of positioning our SoC verification approach as a rare example of a technology that is disruptive yet usable today.
After a very busy six days (two days of booth setup, an all-day company meeting, and three days of exhibits), I finally found an hour or so to wander through the Convention Center and see what other companies had done for the show. I spotted two other booths with professional entertainers, but no musicians. As far as I could tell, in the self-proclaimed Live Music Capital of the World, Breker was the only DAC exhibitor to feature live music in its booth.
Since I did my wandering around wearing the “Breker Man” cape from our skit, I saw lots of double-takes and a few doubling-overs with laughter. My former colleagues at Cadence teased me repeatedly and I’m sure there are incriminating photos somewhere on the Web, but I minded not a bit. The combination of recommendations from Gary Smith and others, Breker’s growing reputation, live music, and a wacky skit that stopped people in their tracks resulted in us gathering more than three times the leads of any previous DAC (or any other show).
Finally, I can’t say enough good things about the decision to hold DAC in Austin. Our lead number speaks for itself and, as I noted in my last post, we saw a lot of local folks who had never attended a DAC before. We had tons of good food, including four of the most famous BBQ joints, and I capped the week off with visits to the Blanton Museum of Art and the incredible Flatbed Press and Gallery before heading to the airport on Thursday. I’m planning a separate post on DAC locations, but for now suffice to say that I hope Austin becomes a regular stop.
Tom A.
The truth is out there … sometimes it’s in a blog.
Tags: Breker, dac, EDA, functional verification, SoC verification
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Tuesday, June 4th, 2013
I’m very tired and a bit giddy as I write this post, late in the evening after the second day of exhibits at the Design Automation Conference (DAC) in Austin. Frankly, a lot of us EDA vendors were concerned about holding DAC in Austin for the first time. Of course there is a large electronics development community in Austin, but the first time in a new location for any conference is always a bit of a gamble since you never know what kind of response you’ll get.
I haven’t seen any statistics for DAC overall yet but I will say right now that the preliminary results for Breker are just amazing. My first scan of the leads we’ve gathered shows this to be our best conference ever both in terms of both quantity and quality. In addition to seeing some old friends we’ve met many engineers from the Austin development centers we had not met before. Most said that they had never attended DAC in previous years but were glad to be able to do so in their own backyard.
One reason for the larger crowds around the Breker booth was a greatly expanded presentation schedule, including a really fun skit. Austin musician and storyteller Rudy Roberson entertained the crowd as the singing captain of the “USS Ice Breker” while yours truly made a special cameo appearance as “Breker Man.” There’s nothing better than some music and a bit of nerdy humor to get people to stop and check out your booth.
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Tags: Breker, dac, EDA, functional verification, SoC verification
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Tuesday, May 28th, 2013
In my previous post on Breker activities at the upcoming Design Automation Conference (DAC) in Austin, I mentioned two verification panels. I’d like to dig a bit deeper on these two panels to encourage EDACafe reader to attend them and also mention a third of possible interest to verification engineers. As a member of this year’s DAC Pavilion Panel Committee, I have a vested interest in seeing a great turnout.
The two panels are:
- “Organizational and Management Solutions to the Verification Crisis” pavilion panel to be held 1:30-2:30pm on Tuesday, June 4 in the DAC Pavilion Theater (Booth 509)
- “Disruptive Verification Technologies: Can They Really Make a Difference?” technical panel to be held 9:00-10:30am on Wednesday, June 5 in Room 16AB
Although DAC has distinct committees for pavilion and technical panels, in practice these two groups work closely together to ensure a strong overall program. The two verification panels above were carefully coordinated so that they address complementary aspects of the “crisis” in which verification is taking up an ever-larger percentage of chip and system development time.
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Tags: Breker, Breker functional verification SoC verification Trek TrekSoC, dac, functional verification, SoC verification
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Tuesday, May 21st, 2013
There’s been some discussion recently in various blogs and forums about the value of print versus digital media for technical publications. Of course this is just a microcosm of a massive shift occurring in the publication industry overall, but I’m going to focus for this post on the sort of technical information once found in physical magazines, industry trade papers, and printed catalogs. All that began to change in the mid 90s as the World Wide Web gained traction and today we live in a very different world than we did just 20 years ago.
A lot of the recent discussion is tied to the decision by technical publisher heavyweight UBM to discontinue print copies of its magazines effective July 1. This was not a huge surprise since UBM stopped printing Electronic Engineering Times late last year. However, that publication had already gone through many changes and no longer much resembled its familiar erstwhile tabloid format. But EDN has been a part of my magazine pile almost since I became an engineer, and more recently Design News and InformationWeek have been part of my regular reading. Apparently Test and Measurement World will no longer exist even in digital form. I will miss all of them.
Of course, I get the majority of my technical and business information online. I subscribe to dozens of different digests, perusing them each morning to catch up on the industry and to cherry-pick interesting items related to SoC verification for tweeting to Breker followers. I’ve never attempted to count them up, but I probably read ten times as many words online every week as I do in print publications. So why have I kept my print subscriptions to the UBM magazines as well as Electronic Design, Chip Design, several ACM and IEEE publications, and more?
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Tags: Breker, functional verification, online, print, publications, SoC verification
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