Posts Tagged ‘emulation’
Monday, June 16th, 2014
We hope you enjoyed last week’s guest post from Jonah McLeod of Kilopass with his experiences at this year’s Design Automation Conference (DAC) in San Francisco. We’ve offered several of our friends in the EDA industry to write in with their assessments of the show. Next up is Lauro Rizzatti, another industry veteran perhaps best-known as general manager of EVE-USA. These days he’s a verification consultant, and he shares his story of going to DAC as a conference attendee rather than as a vendor:
This is the first DAC where I wasn’t responsible for an exhibitor booth and it was exhilarating. I was able to attend sessions, walk the exhibit floor and, generally, get a feel for what’s going on in our industry. I’m pleased to report the news is good. Very good, in fact.
(more…)
Tags: 28nm, Breker, dac, emulation, eve, Flexras, FPGA prototyping, functional verification, Moore's Law, OneSpin, S2C, SoC verification, uniquify
No Comments »
Tuesday, April 15th, 2014
Last week I published a commentary on the Electronic Engineering Times site about the recent growth in the hardware emulation market. I noted that hardware-based platforms have become almost as big a market as software simulation and that some industry projections see them becoming dominant over the next few years. Of course, our friends at Jasper are predicting that formal will become the dominant verification technology, so it will be fun watching a three-way race.
For this post, I want to dig a bit deeper on hardware platforms in general. Historically, such platforms have been divided into three categories: simulation acceleration, in-circuit emulation (ICE), and FPGA prototyping. The reality is that these are no longer clearly distinct categories; there is a lot of fuzziness and even some overlap. While the market for all three types of hardware platforms is growing, I find that my observations and opinions vary depending upon which specific solution I’m considering.
(more…)
Tags: Breker, EDA, emulation, formal analysis, FPGA prototyping, functional verification, jasper, simulation, SoC verification, TrekSoC-Si
No Comments »
Tuesday, April 1st, 2014
In our last post, we discussed some details of the demo that we showed at the DVCon and SNUG Silicon Valley events, in which TrekSoC-Si generated a test case, downloaded it into a commercial SoC (a TI OMAP4430 with dual ARM cores), and ran it in the actual chip. Our focus last time was on Breker’s unique visualization for the multi-threaded, multi-processor test cases that we generate. Specifically, we provide the same display for a test case running in silicon as we do for one running in simulation or simulation acceleration.
Even more interesting is our ability to display coverage information for test cases running in silicon. You might think that this is impossible unless we’re building coverage structures into the SoC that you fabricate. Customers have been known to build specific types of coverage metrics into their hardware, for example real-time monitoring of bus bandwidth and SoC performance. But that’s not what we’re doing; we can gather highly accurate system-level overage without changing the design a bit.
(more…)
Tags: Breker, dvcon, EDA, emulation, functional verification, goals, graph, paths, reuse, scenario model, silicon, simulation, SNUG, SoC verification, system coverage, TrekSoC, use cases
No Comments »
Monday, March 10th, 2014
In our last two posts, we talked about the 2014 edition of the Design & Verification Conference & Exhibition, DVCon, in San Jose. Now that the show is history, lots of bloggers are summarizing their experience. Since I thought that this was an excellent event all around, allow me to join the chorus of voices praising DVCon 2014.
Here at Breker, our biggest effort goes toward the exhibition. Although it’s a relatively small booth and exhibit floor, we do want to put our best foot forward. So we had all-new signage this year updating attendees on our products and their capabilities. We also showed a very different demo from last year, with our TrekSoC-Si product generating a test case, downloading it into a commercial SoC (a TI OMAP4430), and running in the actual chip. We chose to repeat our very popular giveaway from DAC: a combined flashlight and distress whistle that will come in handy if you perform inadequate SoC verification and hit an iceberg.
(more…)
Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, reuse, scenario model, simulation, SoC verification, test generation, TrekSoC-Si
No Comments »
Tuesday, February 25th, 2014
Next week (March 3-6) marks the return of the most important annual event for verification engineers: the Design & Verification Conference & Exhibition 2014, better known as DVCon. Its home remains the DoubleTree hotel in San Jose, a Silicon Valley landmark and site of many interesting conferences going back to its original days as the Red Lion Inn. Breker will be there in force, so we’d like to tell you about our activities as well as preview the technical program.
Of course, Breker will be participating in the exhibition portion of the show. This has expanded from previous years. The exhibit floor will be open on Tuesday (March 4) and Wednesday (March 5) from 2:30pm to 6:00pm as usual. However, a special preview on Monday from 5:00pm to 7:00pm has been added this year. You’ll have plenty of time to stop by to visit Breker in booth number 902 and (if you must) perhaps some other vendors as well.
(more…)
Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, panels, scenario model, simulation, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si
No Comments »
Tuesday, February 4th, 2014
Our last post on the relationship between the Universal Verification Methodology (UVM) and Breker’s technology was very popular. In only a week, it has become the fifth-most-read post in the nine-month history of The Breker Trekker blog. Clearly people are interested in the UVM and what strengths and weaknesses it brings to the ever more complex world of SoC verification.
This week we’d like to continue the discussion with a topic that we did not address last week: how the UVM offers an alternative to running embedded code by replacing one or more of the processors in the SoC with a verification component (VC). Our CEO, Adnan Hamid, addressed this topic in an Electronic Design article last November. We’d like to revisit some of the key points of that article in the context of last week’s UVM discussion
(more…)
Tags: Breker, EDA, emulation, functional verification, reuse, scenario model, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, UVC, uvm, verification component, verification IP, VIP
No Comments »
Tuesday, January 28th, 2014
When people first start reading about Breker and what we do, we make the point that transactional simulation testbenches are breaking down at the full-SoC level. Usually, we specifically mention the Universal Verification Methodology (UVM) standard from Accellera as not being up to the challenge of full-chip verification for SoC designs. We sometimes worry that someone will read into this that we don’t like the UVM, or Accellera, or even standards in general. Nothing could be further from the truth!
We have great respect for the UVM and other EDA-related standards developed by Accellera, IEEE, and other organizations. In this post, we’d like to discuss specifically what we see as the strengths and weaknesses of the UVM and explain how Breker’s technology complements rather than replaces this methodology. Yes, the UVM has limitations, and we address those with our tools and technologies. But the UVM forms a stable and standard base on which nearly all of our customers build their simulation-based verification environments.
(more…)
Tags: Breker, constrained-random, EDA, emulation, functional verification, graph, reuse, scenario model, sequencer, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, Universal Verification Methodology, uvm, VIP, virtual sequencer
No Comments »
Tuesday, January 21st, 2014
Recently on this blog, a series of related posts from Breker, Jasper, and OneSpin discussed formal analysis and its potential for playing a greater role in the verification process. We think that it’s important for The Breker Trekker to address topics in verification beyond our own technology and to provide occasional commentary on technology and the world of EDA in general. However, this recent focus on formal has caused some readers to wonder whether we consider ourselves to be in the formal market.
The short answer is “no” but there is some overlap in the technologies that we use and the techniques employed for formal analysis. Regular readers know that the foundation for our products is a graph-based scenario model that captures both the intended behavior of your SoC design and your system-level test plan. We can automatically extract system coverage from this model, with the model and coverage interacting in interesting ways. Let’s consider to what extent this is formal technology.
(more…)
Tags: Breker, EDA, emulation, formal analysis, functional verification, graph, jasper, OneSpin, scenario model, simulation, system coverage, test generation, TrekSoC, TrekSoC-Si, use cases
No Comments »
Monday, December 30th, 2013
Please allow me to start this post with a sincere wish for all of our readers to have a happy and healthy holiday season. There are many enjoyable activities both sacred and secular this time of year, something for everyone whatever your personal beliefs. I hope that you all have the chance to relax a bit and share some delicious food with family and friends.
I thought about writing a column on the top 5 holiday wishes for verification engineers, but I felt that it would be a bit presumptuous to speak for you. We do work very hard to understand what you need in order to tailor our products to gaps in your verification process and speed up your project. Therefore, I’m going to offer 5 gifts for you, the verification engineer, that are available with Breker’s products. I hope that you like them!
(more…)
Tags: applications, Breker, EDA, emulation, functional verification, graph, production software, reuse, scenario model, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, use cases, uvm, verification IP, VIP
No Comments »
Tuesday, December 17th, 2013
With due apologies to Barbra Streisand, the topic of today’s blog post is the verification of SoC memories and memory subsystems. Once upon a time, memories were considered just about the easiest design structure to verify. A simple automated test doing “walking 1s” and “walking 0s” supplemented by some random reads and write to random addresses with random data seemed to be good enough.
“Can it be that it was all so simple then? Or has time re-written every line?” Actually, it really was that simple back then. But a lot of changes in memory subsystems have come along to complicate matters: memory regions, caches, multi-processor designs, shared memory, complex memory maps, etc. Verification of memories today is much more challenging, with many corner cases to be exercised, but it’s an essential part of the overall SoC verification effort.
(more…)
Tags: Breker, buffer, cache, coherency, constrained-random, emulation, functional verification, graph, memories, memory map, scenario model, streisand, system coverage, TrekSoC, TrekSoC-Si
No Comments »
|
