Posts Tagged ‘EDA’
Thursday, July 14th, 2016
Recently, SemiconductorEngineering published the three–part series “System-Level Verification Tackles New Role” as part of its ongoing “Experts at the Table” discussions. The format is simple–an editor sits down with four or five industry experts to discuss a particular topic–but the debate can be lively and the result educational. Breker participates in these roundtables as often as we can, focusing of course on verification among the many technical topics covered by the site.
In advertising a “new role” for system-level verification, this particular series was not overstating the case. We tend to talk a lot about the evolution of verification in general, especially for system-on-chip (SoC) devices and multi-SoC systems. But in some ways what is happening now with our products and the Accellera portable stimulus standardization effort is more revolutionary than evolutionary. So which is it? We’ll attempt to answer that question in today’s post here on The Breker Trekker blog.
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Tags: acceleration, applications, apps, bandwidth, Breker, cache coherency, Cadence, coverage, debug, EDA, emulation, FPGA prototyping, functional verification, graph, Imperas, mentor, multi-SoC, multi-threaded, multiprocessor, performance analysis, portable stimulus, reuse, scenario model, simulation, SoC verification, system coverage, transactional, TrekApp, TrekBox, TrekSoC, TrekSoC-Si, UVC, uvm
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Tuesday, July 5th, 2016
If the title of today’s post sounds familiar, that’s not surprising. The most popular post in the history of The Breker Trekker blog, by a significant margin, was “An EDA Industry of Startups, Behemoths, Corner Stores, and Zombies?” published almost three years ago. I thought that it would be fun to revisit this topic in light of the changes in the EDA industry over the past three years. Have these changes fundamentally altered our world? Please read on to see.
I’ll begin, as I did in the original post, by noting that the EDA industry used to be divided into only three categories: major leaguers, minor leaguers, and startups. Nearly all EDA startups disappeared after three or four years, with three possible endgames: acquisition, initial public offering (IPO), or bankruptcy. The major leaguers, at one time or another, included Daisy, Mentor, Valid, Cadence, Synopsys, and Avant.
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Tags: acceleration, acquisition, applications, Atrenta, avant, behemoth, Breker, Cadence, corner store, coverage, debug, EDA, functional verification, jasper, M&A, major leaguer, mentor, merger, minor leaguer, portable stimulus, reuse, SoC verification, startup, Synopsys, uvm
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Wednesday, June 29th, 2016
Over the more than three years of posts here on The Breker Trekker blog, you’ve seen us reference our TrekBox runtime component on many occasions. We mention it in many contexts: test case visualization, memory usage visualization, test case status, test case debugging, system-level coverage, performance analysis, I/O interfacing, UVM testbench control, and more. We’ve never had a post on TrekBox itself, so today we rectify that and fill in a few details that we haven’t discussed before.
Some of you are familiar with the term “trickbox” in the context of a simulation testbench. We found a nice concise definition of this term in an ARM patent: “Memory mapped (behavioral) test bench component to facilitate verification.” By writing to designated memory addresses, the processors in the design being verified can send messages to the testbench for various actions. Our TrekBox is of course a play on the “trickbox” name, and it provides many presents inside for those who open it.
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Tags: acceleration, applications, apps, bandwidth, Breker, cache coherency, coverage, debug, duration, EDA, emulation, FPGA prototyping, functional verification, graph, multi-SoC, multiprocessor, performance analysis, portable stimulus, reuse, scenario model, simulation, SoC verification, system coverage, transactional, TrekApp, TrekBox, TrekSoC, TrekSoC-Si, UVC, uvm
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Wednesday, June 22nd, 2016
We have a saying here at Breker that the fundamental job of any EDA company in the functional verification space is to “find more bugs, more quickly.” A good verification solution increases design quality by finding more bugs, improves time to market by closing verification faster, or reduces project cost by requiring fewer resources. A great verification solution, which we strive to offer, does all three. Accordingly, we talk a lot about the type of design bugs we can find with less time and effort than traditional methods.
We have another saying at Breker: “A performance shortfall is a functional bug.” A lot of people differentiate between these two cases, but we don’t agree. The specification for your SoC describes its performance goals as well as its functionality. Not meeting your requirements for latency or throughout can render your SoC unsellable just as surely as a broken feature. So we also talk a lot about how our portable stimulus techniques generate test cases for performance verification.
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Tags: acceleration, applications, apps, bandwidth, Breker, cache coherency, coverage, duration, EDA, emulation, FPGA prototyping, functional verification, graph, latency, performance, performance analysis, portable stimulus, reuse, scenario model, simulation, SoC verification, throughput, transactional, TrekApp, TrekBox, TrekSoC, TrekSoC-Si, UVC, uvm
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Thursday, June 9th, 2016
We’ve just wrapped up the 53rd annual Design Automation Conference (DAC), held for just the second time in Austin. As we mentioned in our show preview last week, Breker was founded in Austin so it’s always nice to return to our roots. With its live music, countless good BBQ joints, and sense of history, Austin is always a fun place to visit. The city has a large high-tech workforce, so we expected crowds similar to those in San Francisco or San Diego.
To be honest, the exhibition floor looked rather quiet at times. With the wide aisles and many attendees clustered around the Big Three EDA vendors and those booths with entertainment or giveaways, other parts of the floor seemed forgotten. Fortunately, our booth was on the major cross aisle and we had the industry momentum around portable stimulus in our favor, so we had a very good show. We’ll discuss our results as we fill in a few highlights from the four days we were there.
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Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, cruise, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, portable stimulus, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP
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Wednesday, June 1st, 2016
The Design Automation Conference (DAC) us nearly upon us once again, this year returning to Austin in just a few days. The first-ever DAC in Austin was held three years ago and it was by all accounts a really good show. It was nice seeing new faces who could carve out an afternoon to visit the exhibit floor but who couldn’t get permission to travel when DAC is elsewhere. We were very pleased by both the number of people who stopped by our booth and their level of interest in what we do.
As you may know, Breker was born in Austin and so it will be a bit of a homecoming for us to return again. Austin features many fun activities, especially musical in nature, and great BBQ restaurants. We’ll be glad to provide suggestions and pointers for these if you ask, but for today’s post we’d like to fill you in what we will be doing at the show this year. We welcome any comments or questions that you may have.
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Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, portable stimulus, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP
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Tuesday, April 19th, 2016
As I discussed at last week, there are many different engineering roles involved in the development of a large, complex semiconductor device. The EDA industry attempts to serve nearly all of these groups, from the architects and product marketing engineers who dream up the new ideas to the technicians who test production parts on the factory floor. Today I’m focusing on the work of two of EDA’s most traditional customer bases: hardware designers and hardware verification engineers.
Perhaps I’d better explain my title. It comes from an old expression “we went to different schools together” that I remember hearing as a youngster. Sometimes this refers to two people who didn’t actually attend the same school but who are nevertheless longtime close friends. But I’ve also heard it used to refer to two people who did in fact go to school together but had very different experiences. This latter context is the one I have mind for design and verification engineers who work on the same project yet inhabit different worlds.
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Tags: Accellera, assertions, Breker, code coverage, coverage, dvcon, EDA, formal analysis, functional coverage, functional verification, graph, graph-based, IP, portable stimulus, PSWG, reuse, scenario model, SemiconductorEngineering, simulation, SoC verification, system coverage, test generator, uvm
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Wednesday, April 13th, 2016
I expect that the activities of the EDA Consortium (EDAC), our industry’s main trade organization, are followed more closely by EDA vendors than users. However, some of you may have seen the recent publicity surrounding the organization’s name change to the Electronic System Design Alliance (ESDA). I applaud this move because it reflects the gradual but ongoing merger of EDA and embedded systems, a topic that we have covered here on The Breker Trekker in the past.
However, I do have two reservations about the specifics of the name change. First, as some people have pointed out, “ESD” is strongly associated with “electrostatic discharge” for us engineers who have worked on actual lab benches and not just in the world of abstract EDA models. But that’s a minor quibble as far as I’m concerned. My bigger issue is that EDAC did not use the name change as a chance to expand from “design” to “development” in its description of scope. Please continue reading as I expand a bit on all three of these points.
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Tags: Bob Smith, Breker, dac, Design Automation Conference, EDA, EDA Consortium, EDAC, embedded systems, ESD Alliance, ESDA, functional verification, graph, graph-based, hardware, IoT, portable stimulus, scenario model, simulation, SoC verification, software
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Tuesday, April 5th, 2016
We try to cover a variety of topics here in The Breker Trekker blog, focusing on technical information but mixing in some general industry analysis as well. Two of our most popular posts of all time have involved the annual semiconductor supplier rankings from IHS, Inc. and the large amount of semiconductor industry merger and acquisition (M&A) activity over the last few years. IHS released their 2015 results yesterday, so it’s time for an update on both of these topics.
Let’s start by catching up on the M&A front. When we last covered this topic in January, the acquisition of Freescale by NXP and the acquisition of Altera by Intel had both just completed late last year. These closed in time to be reflected in the 2015 supplier rankings. There were several other deals from 2015 that were still pending and, while some of them have now closed, their effects will not be seen until the 2016 results are in.
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Tags: Altair, Altera, Apple, Avago, Breker, Broadcom, Cisco, EDA, Freescale, functional verification, Hynix, IHS, Infineon, Intel, Internet of Things, IoT, Leaba, Marvell, MediaTek, mentor, Micron, NVIDIA, NXP, ON, Qualcomm, Renesas, Samsung, SanDisk, semiconductor, Skyworks, SoC, SoC verification, Sony, STMicro, Texas Instruments, TI, Top 20, Toshiba, Western Digital
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Wednesday, March 30th, 2016
For those of us who have been in the EDA business on one side or the other (or both), the Design Automation Conference (DAC) is one of the highlights of every year. I almost hate to admit it, but this year holds DAC number 29 for me. I’ve been to San Francisco, San Diego, Los Angeles, Anaheim, Las Vegas, Dallas, New Orleans, and Orlando, most of them multiple times. But one of the most fun locations was Austin, where DAC was held for the first time three years ago, and where we will return in just a few short months.
There will be plenty of time later for us to fill you in on what Breker will be doing at DAC this year. Since the program for the 53rd annual conference just went live, I thought I’d share some initial impressions and predict some likely highlights. Of course as an exhibitor I’m already deep in planning for the show, but I encourage all of you to review the program and start making your own plans. You’ll be sure to have lots of fun in Austin, and on the basis of the information available today I’m sure that this will be a great show.
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Tags: Accellera, austin, Breker, cache coherency, cloud, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IoT, NoC, portable stimulus, scenario model, simulation, SoC verification, uvm, VIP
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