Posts Tagged ‘dvcon’
Tuesday, February 25th, 2014
Next week (March 3-6) marks the return of the most important annual event for verification engineers: the Design & Verification Conference & Exhibition 2014, better known as DVCon. Its home remains the DoubleTree hotel in San Jose, a Silicon Valley landmark and site of many interesting conferences going back to its original days as the Red Lion Inn. Breker will be there in force, so we’d like to tell you about our activities as well as preview the technical program.
Of course, Breker will be participating in the exhibition portion of the show. This has expanded from previous years. The exhibit floor will be open on Tuesday (March 4) and Wednesday (March 5) from 2:30pm to 6:00pm as usual. However, a special preview on Monday from 5:00pm to 7:00pm has been added this year. You’ll have plenty of time to stop by to visit Breker in booth number 902 and (if you must) perhaps some other vendors as well.
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Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, panels, scenario model, simulation, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si
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Tuesday, November 26th, 2013
The Breker Trekker has been publishing for about seven months now, with 32 posts to date, so running just about once a week. When we started, we committed a new post every two weeks so we’ve been running well ahead of our own expectations. We’re very happy with the growth of our readership and we’d like to take this chance to thank every one of you reading this.
Frankly, we have not been as successful at driving an ongoing dialogue via comments. We’ve had a few comments here and there but not nearly as many as we would like to see. So for this week’s post we’re trying something different: posing a question directly to our readers and heartily encouraging all of you to share your thoughts by leaving a comment at the bottom. Today’s topic: which conferences and trade shows do you find most useful?
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Tags: arrm techcon, Cadence, CDNLive, conference, dac, dvcon, EDA, functional verification, SNUG, Synopsys
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Monday, August 5th, 2013
Back in March I published an opinion piece in Chip Design magazine about redefining “DAC” from “Design Automation Conference” to “Development Automation Conference” and “EDA” from “Electronic Design Automation” to “Electronic Development Automation” to reflect reality. It generated a few comments and got a few people talking but that’s as far as it went.
I certainly didn’t expect a groundswell of support or an overnight change, but I was serious about my reasoning. I think that describing the incredibly complex development process for electronic products as “design” is outdated and not representative of the wide range of skills required.
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Tags: Breker, Cadence, CDNLive, dac, dvcon, EDA, EDAC, functional verification, SNUG, Synopsys
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Tuesday, April 23rd, 2013
As I mentioned in my debut post, this blog will be a mix of technical information, industry commentaries, and updates on Breker and our team. This time I’d like to fill you in on some of the activities that have kept us busy so far in 2013. In the EDA industry, most of the major conferences and tradeshows occur in the first half of the year, while most of the sales happen in the second. That’s not coincidental. New products are introduced at the events, users generally evaluate them in mid-year, and Purchasing departments usually want to close deals before the end of the calendar year.
Accordingly, we at Breker have been very busy with a series of shows in 2013. The biggest event so far was the Design & Verification Conference and Exhibition, better known as DVCon. Held in the San Jose DoubleTree hotel, the focus has shifted over the years to verification, with very little emphasis on design. Perhaps that’s due to another local show called DesignCon about a month earlier. Breker was at DVCon in force, with a spiffy new booth graphic to explain our SoC verification flow.
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Tags: arrm techcon, Breker functional verification SoC verification Trek TrekSoC, dac, dvcon, socc, verfication futures
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