Posts Tagged ‘dac’
Thursday, April 23rd, 2015
Perhaps the biggest cliche in EDA is that functional verification consumes 70% of a chip project’s resources and is growing. Variations on this statistic have been around for at least ten years, probably more. It’s quoted almost as much as Moore’s Law, which incidentally turned 50 this year. Although not as old, the observation that verification dominates SoC development is almost universally accepted. Some may argue the exact percentage, but the spirit remains the same. As a consequence of this state, verification content is turning up everywhere. In today’s post, I’d like to summarize some recent and upcoming events of interest, plus remind you of some related topics covered in previous posts.
My first updates involves DVClub, the informal gathering of verification professionals held in multiple locations around the world. Yesterday was DVClub Silicon Valley, held as usual at Dave & Buster’s mega-arcade in Milpitas. Olig Petlin presented “Formal property verification at AMD: Theory and Practice” to a good-sized crowd. The talk was a nice, comprehensive overview of formal analysis and how it is typically deployed, but I would have liked to hear more specifics about AMD uses it on their projects. Paradigm Works recently assumed management of DVClub in the USA and is doing an excellent job of reinvigorating the franchise with more events in more locations. Boston on May 13 and Austin on June 3 are next on the calendar.
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Tags: Accellera, Breker, dac, Design Automation Conference, DVClub, dvcon, DVCon Europe, DVCon India, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, PSWG, San Francisco, scenario model, simulation, SoC verification, TVS, Universal Verification Methodology, uvm, VIP
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Thursday, April 2nd, 2015
Over the nearly two years we’ve been blogging on The Breker Trekker, some of the most popular posts have been our previews of, and reports from, the annual Design Automation Conference (DAC). The show remains a must-attend event for all EDA vendors and users. One of the key ingredients for its success it that it is really two events in one: a strong technical conference with peer-reviewed papers and a formal Proceedings, plus a busy exhibition floor with vendor booths and suites for prospecting, demos, and update meetings with current customers.
For me personally, it’s almost impossible to imagine not going to DAC. I’ve attended every show since 1988 for at least one of its days, and in many cases for the entire run. DAC stories might be a fun topic for a future post but today I’m going to look ahead rather than back. The technical program for the 52nd DAC was unveiled a few days ago and I’ve been scrolling through the pages on the Web site to see who’s speaking and what topics are hot. This post offers some initial thoughts on sessions likely to be of interest to you, our readers, and a few predictions on what will emerge as the major themes for 2015.
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Tags: Accellera, Breker, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, Universal Verification Methodology, uvm, VIP
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Thursday, December 11th, 2014
Few electronics-related topics have been more widely discussed in the past year or so than the prospects for the so-called Internet of Things (IoT), sometimes called the Internet of Everything (IoE). Hardware and software vendors have been falling all over themselves trying to ride the presumed IoT juggernaut. EDA has not been immune. In its roundup of attendee feedback from this year’s Design Automation Conference (DAC), the DeepChip site quoted a user saying, “The ubiquity of IoT. After 6 hours into DAC, I was ready to slap the next vendor who used that buzzword.”
The trumpeting of IoT was even greater at ARM TechCon, not surprising because of its focus on embedded systems. Here at Breker, we’ve used the term sparingly because it’s not really clear exactly what the IoT will become. Certainly there will be many more nodes of all sorts connected to the Internet in coming years, but there are numerous open questions. Our main interest is whether the IoT will result in an explosion of new SoC designs, and hence a broader market for our verification solutions. This blog post doesn’t provide a firm answer since none is possible yet, but it’s a topic worth addressing.
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Tags: ARM TechCon, Breker, dac, EDA, functional verification, graph, IoE, IoT, reuse, scenario model, SoC verification
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Monday, June 23rd, 2014
Over the last few weeks, we’ve provided a look back at DAC from Breker, Jonah McLeod of Kilopass, and verification consultant Lauro Rizzatti. Today we wind up the series with some great insights and memories from five more DAC exhibitors.
For formal verification services provider Oski Technology, DAC confirmed what it’s experiencing: use of formal adoption is on the rise worldwide, notes Jin Zhang, its senior director of marketing. As is often the case, along with adoption comes the need for training and that’s certainly true for formal verification. Attendees and exhibitors alike stopped by the Oski booth to ask about advanced formal training. Yes, Oski offers several types of training customized to specific needs, and verified that DAC can be a great place to raise awareness and visibility.
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Tags: analog, Breker, dac, EDA, exhibits, functional verification, OneSpin, oski, ProPlus, Spice, startup, uniquify, Verific
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Monday, June 16th, 2014
We hope you enjoyed last week’s guest post from Jonah McLeod of Kilopass with his experiences at this year’s Design Automation Conference (DAC) in San Francisco. We’ve offered several of our friends in the EDA industry to write in with their assessments of the show. Next up is Lauro Rizzatti, another industry veteran perhaps best-known as general manager of EVE-USA. These days he’s a verification consultant, and he shares his story of going to DAC as a conference attendee rather than as a vendor:
This is the first DAC where I wasn’t responsible for an exhibitor booth and it was exhilarating. I was able to attend sessions, walk the exhibit floor and, generally, get a feel for what’s going on in our industry. I’m pleased to report the news is good. Very good, in fact.
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Tags: 28nm, Breker, dac, emulation, eve, Flexras, FPGA prototyping, functional verification, Moore's Law, OneSpin, S2C, SoC verification, uniquify
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Tuesday, June 10th, 2014
Last week, we offered Breker’s perspective on the recently concluded Design Automation Conference (DAC) in San Francisco. After last year’s DAC in Austin, in addition to our own summary we published several guest posts from other vendors in which they shared their impressions of the show. These proved quite popular, and so again this year we’ll be publishing some guest posts with interesting thoughts on DAC and how it’s evolving to meet the needs of the semiconductor industry. Today we begin with Jonah McLeod, director of corporate communications at Kilopass:
Three days of DAC as an attendee found me listening to presentations at the TSMC and SMIC booths from foundry partners. In between times, I listened to two pitches from Monte Carlo simulation vendors Solido Design Automation and CLK Design Automation. Both promised to achieve Spice-level accuracy within a couple of percentage points in a fraction of the time. I also checked out Verifyter AB, a company offering debug automation and analysis software.
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Tags: Breker, CLK, dac, functional verification, IoT, Kilopass, NVM, OTP, SoC verification, Solido, Spice
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Thursday, June 5th, 2014
The 51st Design Automation Conference (DAC) has passed into the history books with three days of exhibits and a wide range of enveloping technical sessions and tutorials. After returning home, I’m thinking back over the week fondly as I nurse feet that ache more than I thought possible. Before I get back into the usual work routine, I want to capture some of the impressions and thoughts running through my head.
There is no doubt that big forces in the industry are aligning toward our view of SoC verification with graph-based scenario models. Many of the people who stopped by our “USS Ice Breker” booth completely understood that they risked hitting an iceberg with their minimal full-chip verification efforts. Some had heard about Breker from colleagues or had seen us listed in Gary Smith’s and John Cooley’s DAC “must see” lists. Others knew little about us but were attracted by our claim as “The SoC Verification Company.” All wanted to know how we can help them.
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Tags: austin, Breker, dac, dvcon, EDA, formal analysis, functional verification, graph, IBM, partnerships, portable stimulus, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si, Verdi
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Wednesday, May 28th, 2014
DAC is back, Jack! The big show returns to San Francisco for two years before heading back to Austin. Last year was a special one for Breker, with our 10th anniversary as a company, the 50th year of DAC, and the first time for the show in Austin, our birthplace. But no location draws more visitors and more buzz than San Francisco. It’s a short train ride from traditional Silicon Valley and arguably part of an extended definition of Silicon Valley that includes a fair chunk of the Bay Area.
This year’s show promises plenty of excitement, and we’d like to fill you in. Of course, we will be there as part of the always lively exhibit floor. Those of you who attended DAC in Austin will surely remember our naval-themed “USS Ice Breker” booth, which we loved so much we’re shipping it to San Francisco. No visit to the DAC exhibits would be complete without stopping by to see Breker in booth 2602 and taking a “cruise” with us. You can request a meeting at a specific time by visiting our DAC signup page.
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Tags: austin, Breker, dac, dvcon, EDA, formal analysis, functional verification, graph, IBM, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si, Verdi
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Tuesday, May 20th, 2014
Many newcomers to Breker’s Web site comment that they are impressed by the quantity and quality of the material located or linked there. For a small company, Breker does publish a lot. Our site links to nearly 250 items from the last two-and-a-half years: conference papers, technical articles, blog posts, press releases, interviews, press coverage, and more. On average, something by or about Breker appears online twice a week, not counting social media alerts or the content hosted on our own site.
Of course this takes a lot of effort by Breker employees, but this level of production would not be possible without the expertise of Nanette Collins, whose marketing and public relations agency has been instrumental in the success of many EDA companies. We thank her for her efforts and welcome her as a guest blogger today. Nanette shares her thoughts on the upcoming (June 2-4) Design Automation Conference (DAC) in San Francisco:
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Tags: Boston Marathon, Breker, dac, EDA, functional verification, marathon, race, SoC verification
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Tuesday, November 26th, 2013
The Breker Trekker has been publishing for about seven months now, with 32 posts to date, so running just about once a week. When we started, we committed a new post every two weeks so we’ve been running well ahead of our own expectations. We’re very happy with the growth of our readership and we’d like to take this chance to thank every one of you reading this.
Frankly, we have not been as successful at driving an ongoing dialogue via comments. We’ve had a few comments here and there but not nearly as many as we would like to see. So for this week’s post we’re trying something different: posing a question directly to our readers and heartily encouraging all of you to share your thoughts by leaving a comment at the bottom. Today’s topic: which conferences and trade shows do you find most useful?
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Tags: arrm techcon, Cadence, CDNLive, conference, dac, dvcon, EDA, functional verification, SNUG, Synopsys
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