Posts Tagged ‘Breker’
Tuesday, April 22nd, 2014
Yesterday may well go down in EDA history as one of the most important days in the evolution of the market for formal analysis. If you had asked me why yesterday morning, I would have said it was because I was attending the third “Decoding Formal Club” meeting sponsored by formal consulting experts Oski Technology. The range of companies represented there, and the enthusiasm for the topic, was a clear indication that formal has become an A-list technology for many verification teams.
So I planned to write today’s post about this meeting. But then, just as it was ending and Oski was thanking all the participants, news broke that Cadence had acquired formal leader Jasper Design Automation for $170M. Of course, this news was of intense interest to the attendees. It made yesterday “Acquisition Day” for formal analysis, so I’ll dub it “A-Day” and provide some thoughts in this post. I will talk a bit about the meeting as well, but will go into more details about the material presented in a future post.
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Tags: 0-In Design Automation, Breker, Cadence, EDA, equivalence checking, formal analysis, functional verification, jasper, mentor, simulation, SoC verification, Synopsys, Verplex
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Tuesday, April 15th, 2014
Last week I published a commentary on the Electronic Engineering Times site about the recent growth in the hardware emulation market. I noted that hardware-based platforms have become almost as big a market as software simulation and that some industry projections see them becoming dominant over the next few years. Of course, our friends at Jasper are predicting that formal will become the dominant verification technology, so it will be fun watching a three-way race.
For this post, I want to dig a bit deeper on hardware platforms in general. Historically, such platforms have been divided into three categories: simulation acceleration, in-circuit emulation (ICE), and FPGA prototyping. The reality is that these are no longer clearly distinct categories; there is a lot of fuzziness and even some overlap. While the market for all three types of hardware platforms is growing, I find that my observations and opinions vary depending upon which specific solution I’m considering.
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Tags: Breker, EDA, emulation, formal analysis, FPGA prototyping, functional verification, jasper, simulation, SoC verification, TrekSoC-Si
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Tuesday, April 8th, 2014
Some readers may recall that I was on the panel “Is Software the Missing Piece In Verification?” at this year’s DVCon. I mentioned a bit about it in my summary of that show, and moderator Ed Sperling has done an outstanding job of transcribing the panel discussion and transforming it into one of his signature “Experts at the Table” three part series on SemiconductorEngineering. I encourage you to read all three parts since a bunch of interesting topics came up.
Cadence recently published an odd blog post that appeared to be based on the panel: it showed a photo of the panelists and included quotes from several of them, although it mentioned neither DVCon nor the panel. Perhaps they were trying to make it sound as if they held a separate event. They quoted their own representative, the panelist from Vayavya, and the panelist from Intel (although they didn’t list his affiliation). But they did hit on one of the more lively topics of the panel: the changing role of the verification engineer.
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Tags: Breker, Cadence, dvcon, embedded programming, functional verification, hybrid, Intel, SoC verification, software-driven verification, Synopsys
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Tuesday, April 1st, 2014
In our last post, we discussed some details of the demo that we showed at the DVCon and SNUG Silicon Valley events, in which TrekSoC-Si generated a test case, downloaded it into a commercial SoC (a TI OMAP4430 with dual ARM cores), and ran it in the actual chip. Our focus last time was on Breker’s unique visualization for the multi-threaded, multi-processor test cases that we generate. Specifically, we provide the same display for a test case running in silicon as we do for one running in simulation or simulation acceleration.
Even more interesting is our ability to display coverage information for test cases running in silicon. You might think that this is impossible unless we’re building coverage structures into the SoC that you fabricate. Customers have been known to build specific types of coverage metrics into their hardware, for example real-time monitoring of bus bandwidth and SoC performance. But that’s not what we’re doing; we can gather highly accurate system-level overage without changing the design a bit.
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Tags: Breker, dvcon, EDA, emulation, functional verification, goals, graph, paths, reuse, scenario model, silicon, simulation, SNUG, SoC verification, system coverage, TrekSoC, use cases
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Tuesday, March 25th, 2014
As we mentioned in our last few posts regarding the DVCon and SNUG Silicon Valley events, Breker exhibited at both shows with an identical demonstration. We showed our latest product, TrekSoC-Si, generating a test case, downloading it into a commercial SoC (a TI OMAP4430 with dual ARM cores), and running in the actual chip. This demonstrated our ability to support all verification platforms, from ESL and RTL simulation through acceleration, emulation, FPGA prototyping, and silicon.
This demo attracted quite a bit of interest and some good questions at both shows, so we thought we’d devote this blog post to filling in a few of the details. We especially want to stress that we provide exactly the same level of visualization for a multi-threaded, multi-processor test case running deep inside an actual chip as we do when it’s running in simulation or simulation acceleration.
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Tags: Breker, dvcon, EDA, functional verification, graph, OMAP, PandaBoard, scenario model, SNUG, SoC verification, Texas Instruments, TI, TrekSoC-Si, use cases
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Wednesday, March 19th, 2014
Perhaps by now you’re tired of reading about DVCon, but our last few posts have drawn very good readership so we know that the show is important to the verification-minded engineers who read The Breker Trekker. Another show, or more accurately a series of shows, has strong verification content and draws well from the verification community. We’re talking about the series of Synopsys Users Group (SNUG) events held worldwide to much acclaim from attendees and participating vendors.
According to the SNUG site, Synopsys has 13 shows scheduled annually in Asia, Europe, and North America, drawing nearly 9000 users. That’s a very impressive series of events by any measure and a sign that the EDA market leader invests heavily in educating its users and providing a forum where they can interact among themselves and with Synopsys technical experts. Next week is the 2014 edition of SNUG Silicon Valley, and we want you to know that Breker will be there.
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Tags: Breker, dvcon, functional verification, SNUG, SoC verification, Synopsys, TrekSoC, TrekSoC-Si, verification IP, VIP
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Monday, March 10th, 2014
In our last two posts, we talked about the 2014 edition of the Design & Verification Conference & Exhibition, DVCon, in San Jose. Now that the show is history, lots of bloggers are summarizing their experience. Since I thought that this was an excellent event all around, allow me to join the chorus of voices praising DVCon 2014.
Here at Breker, our biggest effort goes toward the exhibition. Although it’s a relatively small booth and exhibit floor, we do want to put our best foot forward. So we had all-new signage this year updating attendees on our products and their capabilities. We also showed a very different demo from last year, with our TrekSoC-Si product generating a test case, downloading it into a commercial SoC (a TI OMAP4430), and running in the actual chip. We chose to repeat our very popular giveaway from DAC: a combined flashlight and distress whistle that will come in handy if you perform inadequate SoC verification and hit an iceberg.
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Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, reuse, scenario model, simulation, SoC verification, test generation, TrekSoC-Si
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Tuesday, March 4th, 2014
As we write this post, it’s Tuesday evening and the Design & Verification Conference & Exhibition 2014, DVCon, is halfway over. We could be traditional and have a college marching band entertain us and form schematic diagrams on the field as we wait for the show to resume. We could hire some entertainer whose appeal has faded and who’s willing to do half-time shows to try to resurrect his or her career. But instead we’re going to settle for a simple report.
Monday evening featured, for the first time, an early look at the exhibition floor. DVCon reported that the show has a record number of exhibitors this year, and in fact they spilled out of the DoubleTree ballroom into the lobby. In a time when so many conferences are shrinking, the news that DVCon is growing is most welcome.
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Tags: Breker, dvcon, functional verification, graph, graph-based verification, panel, SoC verification, software-drive verification, TrekSoC, TrekSoC-Si
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Tuesday, February 25th, 2014
Next week (March 3-6) marks the return of the most important annual event for verification engineers: the Design & Verification Conference & Exhibition 2014, better known as DVCon. Its home remains the DoubleTree hotel in San Jose, a Silicon Valley landmark and site of many interesting conferences going back to its original days as the Red Lion Inn. Breker will be there in force, so we’d like to tell you about our activities as well as preview the technical program.
Of course, Breker will be participating in the exhibition portion of the show. This has expanded from previous years. The exhibit floor will be open on Tuesday (March 4) and Wednesday (March 5) from 2:30pm to 6:00pm as usual. However, a special preview on Monday from 5:00pm to 7:00pm has been added this year. You’ll have plenty of time to stop by to visit Breker in booth number 902 and (if you must) perhaps some other vendors as well.
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Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, panels, scenario model, simulation, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si
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Tuesday, February 18th, 2014
In our last post, we discussed the results of a survey by Wilson Research Group and Mentor Graphics. Among other interesting statistics, we learned that verification engineers spend 36% of their time on debug. This seems consistent with both previous surveys and general industry wisdom. As SoC designs get larger and more complex, the verification effort grows much faster than the design effort. The term “verification gap” seems to be on the lips of just about every industry observer and analyst.
We noted that debug can be separated into three categories: hardware, software, and infrastructure. Hardware debug involves tracking down an error in the design, usually in the RTL code. Software debug is needed when a coding mistake in production software prevents proper function. Verification infrastructure–testbenches and models of all kinds–may also contain bugs that need to be diagnosed and fixed. As promised, this post discusses some of the ways that Breker can help in all three areas.
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Tags: Breker, constrained-random, EDA, functional verification, graph, IP, reuse, scenario model, simulation, SoC verification, TrekSoC, TrekSoC-Si, use cases, uvm
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