Posts Tagged ‘austin’
Thursday, June 9th, 2016
We’ve just wrapped up the 53rd annual Design Automation Conference (DAC), held for just the second time in Austin. As we mentioned in our show preview last week, Breker was founded in Austin so it’s always nice to return to our roots. With its live music, countless good BBQ joints, and sense of history, Austin is always a fun place to visit. The city has a large high-tech workforce, so we expected crowds similar to those in San Francisco or San Diego.
To be honest, the exhibition floor looked rather quiet at times. With the wide aisles and many attendees clustered around the Big Three EDA vendors and those booths with entertainment or giveaways, other parts of the floor seemed forgotten. Fortunately, our booth was on the major cross aisle and we had the industry momentum around portable stimulus in our favor, so we had a very good show. We’ll discuss our results as we fill in a few highlights from the four days we were there.
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Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, cruise, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, portable stimulus, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP
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Wednesday, June 1st, 2016
The Design Automation Conference (DAC) us nearly upon us once again, this year returning to Austin in just a few days. The first-ever DAC in Austin was held three years ago and it was by all accounts a really good show. It was nice seeing new faces who could carve out an afternoon to visit the exhibit floor but who couldn’t get permission to travel when DAC is elsewhere. We were very pleased by both the number of people who stopped by our booth and their level of interest in what we do.
As you may know, Breker was born in Austin and so it will be a bit of a homecoming for us to return again. Austin features many fun activities, especially musical in nature, and great BBQ restaurants. We’ll be glad to provide suggestions and pointers for these if you ask, but for today’s post we’d like to fill you in what we will be doing at the show this year. We welcome any comments or questions that you may have.
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Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, portable stimulus, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP
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Wednesday, March 30th, 2016
For those of us who have been in the EDA business on one side or the other (or both), the Design Automation Conference (DAC) is one of the highlights of every year. I almost hate to admit it, but this year holds DAC number 29 for me. I’ve been to San Francisco, San Diego, Los Angeles, Anaheim, Las Vegas, Dallas, New Orleans, and Orlando, most of them multiple times. But one of the most fun locations was Austin, where DAC was held for the first time three years ago, and where we will return in just a few short months.
There will be plenty of time later for us to fill you in on what Breker will be doing at DAC this year. Since the program for the 53rd annual conference just went live, I thought I’d share some initial impressions and predict some likely highlights. Of course as an exhibitor I’m already deep in planning for the show, but I encourage all of you to review the program and start making your own plans. You’ll be sure to have lots of fun in Austin, and on the basis of the information available today I’m sure that this will be a great show.
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Tags: Accellera, austin, Breker, cache coherency, cloud, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IoT, NoC, portable stimulus, scenario model, simulation, SoC verification, uvm, VIP
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Tuesday, December 22nd, 2015
In last week’s blog post, I reported from the recent 16th International Workshop on Microprocessor Test and Verification (MTV) in Austin. I focused mostly on the panel “Portable Stimulus and Testbenches – Possibilities or Wishful Thinking?” that included representatives from ARM, Cadence, Mentor, Synopsys, Freescale (now NXP), and Breker (yours truly). The panel was most enjoyable, but only one of several highlights for me at MTV.
This week, I’d like to touch briefly on some of the talks and topics on the technical program that caught my ear. These reflected a number of research frontiers for verification as well as several real-world case studies of SoC design projects tackling tough verification challenges. Perhaps the best moment for me was hearing Altera, one of our customers, describe how they used our products successfully on a recent design.
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Tags: Accellera, AMD, ARM, austin, Avago, Breker, Cadence, EDA, FPGA, Freescale, functional verification, graph, graph-based, mentor, MTV, node, NVIDIA, portable stimulus, PSWG, scenario model, simulation, SoC verification, Sudoku, Synopsys, test generator
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Wednesday, December 16th, 2015
Do you want to hear all the behind-the-scenes dirt from a workshop on the future of the MTV cable channel? Well, you’ll have to look elsewhere. “MTV” in this case means the International Workshop on Microprocessor Test and Verification, which celebrated its 16th incarnation in Austin two weeks ago. Although the name of the workshop has officially expanded to “Microprocessor and SOC Test and Verification” rest assured that the delightfully ambiguous abbreviation “MTV” will remain.
This was only my second time at this event, but I wish that I had been able to attend more. The setting is the top floor of the Hyatt Regency, with great views of Lady Bird Lake (formerly Town Lake) and downtown Austin. However, I noticed that recent high-rise construction has now blocked the sight of the Texas State Capitol from the hotel. The view might be distracting if not for the fact that the technical committee put together an interesting and diverse program, including a panel on portable stimulus.
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Tags: Accellera, ARM, austin, Breker, Cadence, EDA, emulation, FPGA, Freescale, functional verification, graph, graph-based, horizontal reuse, mentor, MTV, node, portable stimulus, PSWG, scenario model, silicon, simulation, SoC verification, Synopsys, test generator, vertical reuse
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Tuesday, September 9th, 2014
What verification engineer doesn’t love the occasional conference? It’s a chance to get out of the cubicle farm, hang out with colleagues from other companies, listen to stimulating technical talks, and catch up on what EDA, IP, and semiconductor vendors have been doing. Even in a time of tight travel budgets, the right conference can provide dividends far beyond its cost. There are a lot of smart people in the electronics industry and it’s valuable to share problems and solutions with them.
There are actually quite a few conferences and trade shows that have interesting verification content and draw significant numbers of verification engineers. One of the most-read posts in the history of The Breker Trekker blog was a discussion on which conferences verification engineers like best. We are constantly evaluating which events provide the most value to us and our customers, and find ourselves in the unusual position of having four shows scheduled in four locations over the next four weeks.
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Tags: Accellera, apps, ARM, austin, Bangalore, Boston, Breker, Cadence, coherency, CVC, DV, dvcon, ESL, functional verification, India, mentor, Newton, portable stimulus, Santa Clara, SNUG, Synopsys, TechCon, TrekSoC, TrekSoC-Si, TrekUVM, uvm
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Thursday, June 5th, 2014
The 51st Design Automation Conference (DAC) has passed into the history books with three days of exhibits and a wide range of enveloping technical sessions and tutorials. After returning home, I’m thinking back over the week fondly as I nurse feet that ache more than I thought possible. Before I get back into the usual work routine, I want to capture some of the impressions and thoughts running through my head.
There is no doubt that big forces in the industry are aligning toward our view of SoC verification with graph-based scenario models. Many of the people who stopped by our “USS Ice Breker” booth completely understood that they risked hitting an iceberg with their minimal full-chip verification efforts. Some had heard about Breker from colleagues or had seen us listed in Gary Smith’s and John Cooley’s DAC “must see” lists. Others knew little about us but were attracted by our claim as “The SoC Verification Company.” All wanted to know how we can help them.
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Tags: austin, Breker, dac, dvcon, EDA, formal analysis, functional verification, graph, IBM, partnerships, portable stimulus, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si, Verdi
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Wednesday, May 28th, 2014
DAC is back, Jack! The big show returns to San Francisco for two years before heading back to Austin. Last year was a special one for Breker, with our 10th anniversary as a company, the 50th year of DAC, and the first time for the show in Austin, our birthplace. But no location draws more visitors and more buzz than San Francisco. It’s a short train ride from traditional Silicon Valley and arguably part of an extended definition of Silicon Valley that includes a fair chunk of the Bay Area.
This year’s show promises plenty of excitement, and we’d like to fill you in. Of course, we will be there as part of the always lively exhibit floor. Those of you who attended DAC in Austin will surely remember our naval-themed “USS Ice Breker” booth, which we loved so much we’re shipping it to San Francisco. No visit to the DAC exhibits would be complete without stopping by to see Breker in booth 2602 and taking a “cruise” with us. You can request a meeting at a specific time by visiting our DAC signup page.
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Tags: austin, Breker, dac, dvcon, EDA, formal analysis, functional verification, graph, IBM, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si, Verdi
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Tuesday, September 24th, 2013
I had planned to write today about the TrekBox module, an essential part of TrekSoC that links the code running in the embedded processors with the I/O pins of an SoC. But, in the course of reviewing my various daily news digests, I read the curiously titled blog post “Tightlipped Unicorns & Monochrome Rainbows” on the Electronic Engineering Times site. It moved my thoughts in other directions entirely, so here is the result.
In the post, Radfan CTO Simon Barker argues that startups should be more honest about the challenges they face in order to obtain help or advice from those who’ve already lived through such adventures. He maintains that company founders who automatically say “Great!” when asked how things are going are missing an opportunity to garner such assistance and are wasting their time at startup events. This position triggered three major lines of thought for me.
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Tags: accountability group, advisers, austin, Breker, EDA, functional verification, startup
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Friday, June 14th, 2013
I spent my last few posts previewing and reporting on the 50th Design Automation Conference (DAC) in Austin. As I have mentioned, this was the first time that DAC was held in Austin and so a lot of vendors were nervous about that. I know at least a couple of companies who downsized their DAC crews in anticipation of a smaller show. Well, the numbers are in and DAC did fairly well in Austin. Full-conference passes were 1589, down 16% from 2012 in San Francisco. Exhibits-only passes were 2364, down 15%. The number of both staffers was down 26%, reflecting both consolidation in the EDA industry and smaller crews.
No one really expected Austin to match San Francisco, but the numbers are quite respectable. What was especially interesting was that the number of exhibits-only passes exceeded by 15% those in San Diego in 2011. It seems that the local electronics community really turned out at DAC this year, already clear to us exhibitors since we saw many new faces we had not seen at shows in other locations.
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Tags: austin, Breker, dac, EDA, functional verification, SoC verification
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