Archive for the ‘Uncategorized’ Category
Monday, August 19th, 2013
No SoC verification engineer worthy of the title would argue that coverage is unimportant. Even back in the 1980s, before commercial coverage tools and industry standards were available, leading ASIC teams manually added coverage code into their testbenches. They checked that key state machines visited all legal states or made all legal transitions, or that a processor executed all opcodes in its instruction set, over the course of a simulation test.
Verification teams who ignored coverage in those days were at risk of letting bugs slip through to silicon. The old maxim “if you don’t verify it, it’s broken” summed the situation up well. Today, leading SoC teams have adopted system coverage. Those who are ignoring this aspect of coverage are at risk of letting serious system-level bugs slip through. Let’s talk about system coverage and why it’s different from other metrics in use today.
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Tags: Breker, code coverage, concurrency, coverage, functional coverage, functional verification, graph, scenario model, SoC verification, system coverage, TrekSoC
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Monday, August 12th, 2013
The electronics industry is still buzzing over the first Design Automation Conference (DAC) held in Austin in June. Bob Smith, Senior Vice President of Marketing and Business Development at Uniquify, offers his perspective:
The Uniquify team looked at this year’s DAC through the Ray-Ban-like sunglasses we used as giveaways and liked what we saw. Exhibitors had cautious optimism prior to this year’s conference and Austin didn’t disappoint. All in all, everyone seemed delighted to be in the capital of the Lone Star State.
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Tags: Breker, dac, EDA, IP, services, uniquify, willie nelson
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Monday, August 5th, 2013
Back in March I published an opinion piece in Chip Design magazine about redefining “DAC” from “Design Automation Conference” to “Development Automation Conference” and “EDA” from “Electronic Design Automation” to “Electronic Development Automation” to reflect reality. It generated a few comments and got a few people talking but that’s as far as it went.
I certainly didn’t expect a groundswell of support or an overnight change, but I was serious about my reasoning. I think that describing the incredibly complex development process for electronic products as “design” is outdated and not representative of the wide range of skills required.
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Tags: Breker, Cadence, CDNLive, dac, dvcon, EDA, EDAC, functional verification, SNUG, Synopsys
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Monday, July 29th, 2013
The recent guest post from OneSpin looking back at the Design Automation Conference (DAC) in Austin was very popular, so we’ve invited some more of our friends from the EDA community to share their experiences. This week we hear from Lianfeng Yang, Vice President of Marketing at ProPlus Design Solutions, Inc.:
This year’s DAC proved to be a journey from Nano-scale SPICE modeling to Giga-scale SPICE simulations and a place where attendees could learn the secrets of design for yield (DFY) during a Wednesday afternoon pavilion panel.
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Tags: Breker, BSIMPro, BSIMProPlus, dac, DFY, EDA, functional verification, ProPlus
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Tuesday, July 23rd, 2013
Folks who have been following Breker for a while know that we like the phrase “begin with the end in mind.” It succinctly summarizes why our use of graph-based scenario models is different than traditional constrained-random testbenches.
Suppose that you want to trigger a particular behavior within your design as part of your verification process. With a testbench, you have control over only the design’s inputs, so you might issue a series of input stimulus changes that you believe will cause the desired behavior. You may hit your target, or you may not. Automating your testbench with the constrained-random capabilities of the Universal Verification Methodology (UVM) reduces the manual effort, but there’s still no guarantee that you will trigger your targeted behavior.
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Tags: Breker, constrained-random, EDA, functional verification, graph, scenario model, test generation, TrekSoC, uvm
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Tuesday, July 16th, 2013
As you may have noticed, we call Breker “The SoC Verification Company” because we truly believe that we are defining a new category of EDA tools for SoC verification that has not been adequately addressed by other approaches. In the spirit of an engineer defining his or her terms before use, and with a nod to the long-running TV game show Jeopardy, let’s discuss what defines SoC verification and why it is different from verification of IP blocks and other types of chips.
Let’s start one clue higher on the Jeopardy board, with “SoC” for $400. What exactly is a system on chip (SoC)? Some would argue that any large, complex chip qualifies. We beg to differ. Should a pure processor, no matter how powerful, be called an SoC? Alternatively, should a giant network crossbar switch with no central processor be considered an SoC? The Breker viewpoint says that neither qualifies. We believe that an SoC contains at least one reasonably powerful embedded processor (8-bit MCUs don’t count) and multiple IP blocks interconnected by some sort of bus or fabric.
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Tags: Breker, EDA, functional verification, integration verification, jeopordy, SoC, SoC verification, TrekSoC
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Tuesday, July 9th, 2013
As you have read, Breker had an excellent Design Automation Conference (DAC) this year. Many other EDA vendors were pleased as well. Today, guest blogger Dr. Raik Brinkmann from OneSpin Solutions shares his experience:
After sitting out DAC last year, OneSpin Solutions was back, exhibiting and demonstrating our innovative formal assertion-based verification and formal equivalence checking solutions. Overall, we considered the 50th DAC to be a great success. From what we heard, we weren’t alone in our assessment. The exhibit floor was busy all three days and the technical sessions hopping. In general, most of the exhibitors were happy with attendance and thought DAC was worthwhile. No one knew what to expect, given the Austin location and the general health of the economy and EDA industry.
We’re pleased with the number of leads we collected from DAC and attribute much of it to our pre-DAC marketing and public relations campaign. We started upping our visibility around November last year and went into high gear at DVCon earlier this year. I highly recommend this strategy to all DAC exhibitors for next year.
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Tags: cloud, dac, EDA, equivalence checking, functional verification, integration verification, OneSpin
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Tuesday, July 2nd, 2013
A year or two ago, cloud computing was a hot topic at EDA events and conferences. The industry’s largest player, Synopsys, talked a lot about running their EDA tools in the cloud and claimed a great deal of customer interest in this area. Earlier this year, CEO Aart de Geus was quoted as saying that “Synopsys had made $0 on it.” What happened? Is the idea of EDA in the cloud dead? What are the issues preventing its adoption?
In talking to customers and reading related articles, I’ve heard of several reasons why the cloud is not yet a factor for EDA. One practical issue is that EDA vendors are not sure how to price cloud-based licenses. If the customer motivation to move to the cloud is to more easily handle infrequently used tools or to provide peak capacity for frequently used tools, indeed the wrong pricing model could cost the vendor money. One technical issue is that some EDA tools are interactive and would be painful to use over the Internet.
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Tags: Breker, Cadence, cloud computing, EDA, functional verification, SoC verification
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Tuesday, June 18th, 2013
Back before DAC, I wrote a blog post on the rapid migration of technical information from magazines and catalogs to online-only publication. I addressed the topic from my perspective as a voracious reader of industry news who likes flipping through magazines as a nice break from staring at the screen most of the day. Just for the record, today over lunch I skimmed through the latest hardcopy issues of Information Week, Electronic Design, and MIT’s Spectrum. But my post also addressed a more serious topic: the evanescence of online technical content.
Futurists would have us believe otherwise: online is supposed to be forever. However, many technical sites are hosted by motivated individuals or organizations who may simply decide one day to stop. Other sites are owned by commercial interests, including publishers, who may fold and take their content with them into the void. Yes, there are organizations trying to capture the ongoing history of the Internet but, in my experience, their retention of desired content is inconsistent at best.
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Tags: Breker, dac, EDA, online, print, publications, SoC verification
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Friday, June 14th, 2013
I spent my last few posts previewing and reporting on the 50th Design Automation Conference (DAC) in Austin. As I have mentioned, this was the first time that DAC was held in Austin and so a lot of vendors were nervous about that. I know at least a couple of companies who downsized their DAC crews in anticipation of a smaller show. Well, the numbers are in and DAC did fairly well in Austin. Full-conference passes were 1589, down 16% from 2012 in San Francisco. Exhibits-only passes were 2364, down 15%. The number of both staffers was down 26%, reflecting both consolidation in the EDA industry and smaller crews.
No one really expected Austin to match San Francisco, but the numbers are quite respectable. What was especially interesting was that the number of exhibits-only passes exceeded by 15% those in San Diego in 2011. It seems that the local electronics community really turned out at DAC this year, already clear to us exhibitors since we saw many new faces we had not seen at shows in other locations.
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Tags: austin, Breker, dac, EDA, functional verification, SoC verification
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