What Can PSS Do For You? See Breker’s Demos of Trek5’s Capabilities at DVCon

All of us at Breker invite DVCon attendees to step into our booth (#701) and expect to be amazed. You will see practical demonstrations of our new feature-rich Trek5 with practical examples of how the Portable Stimulus Standard can be applied to accelerate UVM coding for complex blocks and Software Driven Verification (SDV) for large SoCs.

Yes, I’m proud of Trek5 and boasting a bit. Trek5 doesn’t stop at just Portable Stimulus synthesis –– it’s a complete solution that can be deployed across the verification spectrum. We went well beyond a simple conversion of PSS models to tests that required users to perform a lot of hand codinging. Instead, we automated the process, simplifying UVM stimulus, scoreboard and coverage authoring for complex blocks and SDV, complete with portable system services, for SoCs.

While classic PSS model solving is part of Trek5’s repertoire, its Test Suite Synthesis capabilities now allow tests to be optimized for UVM block verification, SDV and Post-Silicon environments. Its unique TrekDebug tool enables post-verification debug, profiling and automated coverage closure.

Our Trek5 tool suite is comprehensive and includes TrekGen™ for PSS-based test suite synthesis, TrekUVM™, TrekSoC™ and TrekSoC-Si™ deployment optimizers, TrekDebug™ for post-verification analysis, the TrekDesigner™ graphical entry tool and a range of TrekApps™.

Here’s a tantalizing look at what our demos will highlight:

Several features alleviate the need for end users to write excessive SystemVerilog and C code into their PSS models to generate testbench code. TrekGen, for example, is a Test Suite Synthesis tool that takes PSS models as input in both the Domain Specific Language (DSL) and C++ variants of the Accellera Portable Stimulus Standard . It allows path constraints and path coverage to be applied across standard scenario models and includes advanced procedural support for power users. TrekDesigner comes with TrekGen. It’s a graphical entry tool with a full range of pre-verification analysis capabilities for reachability, coverage and test inspection.

Trek5 is further differentiated with a range of deployment optimizers for three flows –– UVM, SDV and post-silicon –– designed to be cross-flow portable. These unique solutions allow allow Portable Stimulus-generated tests to be deployed directly into existing test environments with minimal additional effort.

Complex sequences, coverage and scoreboards are optimized by TrekUVM using test scheduling synthesis and other capabilities for existing UVM environments. This is useful for larger blocks with multiple I/O ports because it allows multi-threaded, synchronized sequence streams to be generated from a single, easy-to-understand, white-box scenario specification.

TrekSoC includes a Hardware Software Interface (HSI) that affords OS-like micro-kernel services to simplify bare-metal processor C tests. Also included is advanced memory allocation testing, TrekBox backdoor memory access and other capabilities. This enables multi-threaded processor C tests and I/O transactions to be transparently generated for SoC designs without end-user integration effort, tracking down complex corner cases hard to envisage by hand. Simulation and emulation variants are included.

Diagnostic tests are supplied by TrekSoC-Si for post-fabricated silicon or field programmable gate array (FPGA) prototyping systems that make use of the same verification scenario tests. TrekSoC-Si includes hardware access so that the same environment can be used as with the Trek verification solutions, providing visibility and simplifying test monitoring and analysis.

Another unique tool from Breker is TrekDebug. It allows self-checking, multi-threaded tests to be monitored and debugged, along with full coverage analysis and design profiling and optimization. This solution accesses common signal-level debuggers, such as Synopsys’ Verdi, to accelerate the debug process.

TrekApps provide solutions to common verification tasks, including cache coherency, ARMv8 installation testing and power-management analysis with more to follow. They deliver fully configurable test environments without the need to understand the PSS languages.

DVCon will be held Monday, February 25, through Thursday, February 28, at the DoubleTree Hotel in San Jose, Calif. More information can be found at: www.dvcon.com

For more enticement, we will be all over DVCon this year. You can see practical applications for Trek5 during several sessions in the program:

• I will be a panelist on “Verification and Compliance in the era of open ISA –– Is the Industry ready to Address the Coming Tsunami of Innovation?” Wednesday from 8:30 a.m. until 9:30 a.m.
• “Product Life Cycle of Interconnect Bus: A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation” will be presented by Gaurav Bhatnagar, staff engineer at Analog Devices. He will discuss a PSS methodology using Trek during the “Applications of the new Portable Stimulus Standard” session Wednesday from 10 a.m. until noon.
• Breker and Willamette HDL will offer a workshop titled, “Using Portable Stimulus to Verify an ARMv8 Sub-System Integration on an SoC,” Thursday from 1p.m. until 2:30 p.m. It will include an overview of the Accellera PSS language and a detailed plan for verifying an ARMv8 sub-system integration using Trek5.

Yes, we believe Trek5 is amazing, dazzling, tantalizing and enticing. Showing how Accellera’s PSS can provide practical solutions that take the pain out of verification is our goal for this year’s DVCon!

Tags: ARMv8, Breker, C++, DSL, portable stimulus, Post-Si Flow, RISC-V, SDV FLow, Trek5, TrekApps, TrekDebug, TrekDesigner, TrekSoC, TrekSoC-Si, TrekUVM, UVM Flow

This entry was posted on Thursday, February 21st, 2019 at 1:27 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.