User Victory in Portable Stimulus

As regular readers know, the Portable Stimulus Working Group (PSWG) of the Accellera System Initiative has been working for some time to develop a new way to define verification intent once and to be able to reuse that across all stages of the verification flow and to be able to reuse it across designs. This will dramatically increase verification efficiency and establish verification methodologies that are likely to be used for the next couple of decades.

While standards bodies normally keep quiet about the internal workings of their committees, there have been unauthorized leaks recently that provided some inaccurate information and we would like to set the record straight in this blog and to tell the verification community that they have achieved a significant victory. This demonstrates the importance of users voicing their concerns during the development of standards.

As has been revealed publicly in standards updates at several conferences, the PSWG has been considering two alternative formats for the specification of the portable stimulus model. The first is a new domain-specific language (DSL) defined expressly for this standard. Cadence and Mentor have been the main authors and proponents of this proposal. The other proposal, driven primarily by Breker, with important contributions from several user companies, is based on the C++ standard.

It has been revealed that while a DSL will be developed, there will be a second representation based on C++. This is being included because, as reported by Tom Fitzpatrick, committee vice chair, “there is a large contingent of potential users who prefer writing their tests in C++.” We are proud that Breker has been the advocate for the users in these discussions and will continue to ensure that users are given the choice that they have been asking for.

Your victory is even more important than it may at first appear. First, it means that the DSL is superfluous because C++ will be capable of semantically describing everything necessary for portable stimulus. Some EDA vendors may prefer to add syntactic sugar or graphical representations on top of the core semantics, but the user can be assured that they will never be trapped into any vendor’s implementation because everything will be expressible in a language that has been an industry standard for decades. The committee vice chair agrees saying that “by having the standard support both input formats, and ensuring their interoperability and semantic equivalence, we will have portability between users and between vendors, as well as the inter- and intra-project portability that is the main technical goal of the WG.”

It is fairly self-evident why users wanted C++ so badly. Consider for a moment the five stage holders within an organization: IP verification, full chip verification, emulation and FPGA prototyping, post silicon, and driver development. Apart from the first, all of these have one common element and that is that C++ is central to their purpose. No chip is developed today that is not a mix of hardware and software and no chip can be verified without bringing in some elements of the controlling software. Emulation and FPGA prototyping are all about the verification of software, as is post silicon verification. In addition, most companies are trying to develop and integrate their drivers much earlier in the design flow than they have in the past. These groups understand C++ and do not need, or want, a new language. IP-level verification engineers do not deal much with C/C++, and so a streamlined SystemVerilog-like DSL may be attractive for them.

The standard is far from complete at this stage, but the direction is now clear. Both proposals will continue to evolve as we find the best ways to meet the requirements as defined for the standard. The C++ solution has already been extended with some of the ideas from the DSL proposal, but there is also capability in our proposal that they cannot yet match. It is critical for a successful standard that we do not reduce the capabilities of a C++ format to match the limitations of the DSL proposal. If you agree, please comment and consider joining the PSWG to help create the best possible standard.

Tags: Accellera, Breker, EDA, functional verification, IBM, NVIDIA, portability, portable stimulus, portable stimulus market leader, PSWG, reuse, SoC verification, software-driven verification, test generation, user advocate, verification efficiency, verification IP, verification methodology

Category: Knowledge Depot

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