Archive for June, 2016
Wednesday, June 29th, 2016
Over the more than three years of posts here on The Breker Trekker blog, you’ve seen us reference our TrekBox runtime component on many occasions. We mention it in many contexts: test case visualization, memory usage visualization, test case status, test case debugging, system-level coverage, performance analysis, I/O interfacing, UVM testbench control, and more. We’ve never had a post on TrekBox itself, so today we rectify that and fill in a few details that we haven’t discussed before.
Some of you are familiar with the term “trickbox” in the context of a simulation testbench. We found a nice concise definition of this term in an ARM patent: “Memory mapped (behavioral) test bench component to facilitate verification.” By writing to designated memory addresses, the processors in the design being verified can send messages to the testbench for various actions. Our TrekBox is of course a play on the “trickbox” name, and it provides many presents inside for those who open it.
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Tags: acceleration, applications, apps, bandwidth, Breker, cache coherency, coverage, debug, duration, EDA, emulation, FPGA prototyping, functional verification, graph, multi-SoC, multiprocessor, performance analysis, portable stimulus, reuse, scenario model, simulation, SoC verification, system coverage, transactional, TrekApp, TrekBox, TrekSoC, TrekSoC-Si, UVC, uvm No Comments »
Wednesday, June 22nd, 2016
We have a saying here at Breker that the fundamental job of any EDA company in the functional verification space is to “find more bugs, more quickly.” A good verification solution increases design quality by finding more bugs, improves time to market by closing verification faster, or reduces project cost by requiring fewer resources. A great verification solution, which we strive to offer, does all three. Accordingly, we talk a lot about the type of design bugs we can find with less time and effort than traditional methods.
We have another saying at Breker: “A performance shortfall is a functional bug.” A lot of people differentiate between these two cases, but we don’t agree. The specification for your SoC describes its performance goals as well as its functionality. Not meeting your requirements for latency or throughout can render your SoC unsellable just as surely as a broken feature. So we also talk a lot about how our portable stimulus techniques generate test cases for performance verification.
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Tags: acceleration, applications, apps, bandwidth, Breker, cache coherency, coverage, duration, EDA, emulation, FPGA prototyping, functional verification, graph, latency, performance, performance analysis, portable stimulus, reuse, scenario model, simulation, SoC verification, throughput, transactional, TrekApp, TrekBox, TrekSoC, TrekSoC-Si, UVC, uvm No Comments »
Wednesday, June 15th, 2016
In the last few days before DAC, as I was worrying about booth setup and demo practice, an important press release flashed by. The opening paragraph really should have caught my eye immediately: “Arrow Electronics, Inc. (NYSE: ARW) announced today that it has signed a definitive agreement to acquire the global internet media portfolio focused on technology and electronic design from UBM, including EE Times, EDN, ESM, Embedded, EBN, TechONline, and Datasheets.com.”
Perhaps this news doesn’t seem especially important to many readers, but to observers of the electronics trade press this is a big deal. The titles listed above are some of the best-known brands in the business. Arrow is an electronics distributor and services provider with a fine reputation, but it is not a traditional publisher. This industry transition has given me pause so I will make a few observations and then solicit your thoughts.
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Tags: Arrow, blog, Breker, ee journal, EE Times, electronics trade press, functional verification, Goering, journalism, portable stimulus, print, publishing, uvm 4 Comments »
Thursday, June 9th, 2016
We’ve just wrapped up the 53rd annual Design Automation Conference (DAC), held for just the second time in Austin. As we mentioned in our show preview last week, Breker was founded in Austin so it’s always nice to return to our roots. With its live music, countless good BBQ joints, and sense of history, Austin is always a fun place to visit. The city has a large high-tech workforce, so we expected crowds similar to those in San Francisco or San Diego.
To be honest, the exhibition floor looked rather quiet at times. With the wide aisles and many attendees clustered around the Big Three EDA vendors and those booths with entertainment or giveaways, other parts of the floor seemed forgotten. Fortunately, our booth was on the major cross aisle and we had the industry momentum around portable stimulus in our favor, so we had a very good show. We’ll discuss our results as we fill in a few highlights from the four days we were there.
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Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, cruise, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, portable stimulus, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP No Comments »
Wednesday, June 1st, 2016
The Design Automation Conference (DAC) us nearly upon us once again, this year returning to Austin in just a few days. The first-ever DAC in Austin was held three years ago and it was by all accounts a really good show. It was nice seeing new faces who could carve out an afternoon to visit the exhibit floor but who couldn’t get permission to travel when DAC is elsewhere. We were very pleased by both the number of people who stopped by our booth and their level of interest in what we do.
As you may know, Breker was born in Austin and so it will be a bit of a homecoming for us to return again. Austin features many fun activities, especially musical in nature, and great BBQ restaurants. We’ll be glad to provide suggestions and pointers for these if you ask, but for today’s post we’d like to fill you in what we will be doing at the show this year. We welcome any comments or questions that you may have.
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Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, portable stimulus, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP No Comments »
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