Riding the Portable Stimulus Wave

Last week, we discussed the details of a noteworthy press release that we issued with Cadence and Mentor Graphics announcing a joint contribution to the Portable Stimulus Working Group (PSWG) of Accellera Systems Initiative. As we expected, this release stirred up a lot of interest in portable stimulus. The timing was perfect, both because of today’s deadline for contributions to the PSWG and because of last week’s DVCon India conference. I’d like to provide some updates on both activities.

First of all, the three companies did upload our joint contribution document to the PSWG internal Web site today in time for the deadline. Please note that, as per the rules for Accellera and most other standards groups, working documents are not available to the general public. If you’d like to see the contribution and follow the evolution of the standard, please consider joining the PSWG. If your company is not yet a member of Accellera, then please alert your standards manager to the benefits of participation.

Let me again thank our colleagues at Cadence and Mentor for their willingness to collaborate on a joint contribution. In addition to our post, they also published some nice commentary on this effort. At last week’s DVCon India, I was joined by Mentor’s Dennis Brophy and Nick Heaton from Cadence at a special “Birds of a Feather” (BoF) breakfast session on portable stimulus. It was a rare chance to stand side by side with competitors presenting a unified message in support of more rapid standardization.

Even though the BoF was on Friday at 8:00 am, well before the 9:30 am start of regular conference sessions, the room was packed to the walls with about 70 people. At least another dozen or two peeked in but decided that there was no room to join. The questions from the audience were thoughtful and on point. Quite a few of the engineers who stopped by our booth later in the day said that their interest was heightened by the BoF.

We joined Mentor Graphics and Vayavya Labs in the “Leveraging Portable Stimulus across Domains and Disciplines” tutorial. Although each of the three talks covered different aspects of the problem, all were clear that graph-based models were essential to the solution and that faster coverage convergence is one of the benefits. This session was also well attended, with about 65 people filling most of the room. The other presenters and I held a joint Q&A session at the end, and the questions from the audience were excellent.

Portable stimulus also took center stage at a third event, a technical session in the design and verification (DV) track. Sandeep Korrapati from IBM India presented an outstanding talk on “Walking the Graph” that discussed how they use our Trek family of products to verify their very large chips. Our partner CVC presented a case study on coverage closure, also using our Trek tools. Finally, Xilinx and Mentor Graphics also discussed the use of graph-based techniques. As at the BoF, every seat was full and there were a number of late arrivals standing.

The customers and prospects who stopped by our booth were almost entirely focused on learning more about portable stimulus. It was quite busy at times, so I want to thank our Indian distributor Delphinium for helping to staff the booth. There were lots of questions about the joint press release as well. At one customer meeting in Bangalore prior to the show, we talked about how Breker, Cadence, and Mentor were joining forces for a contribution. The Director of Engineering’s response? “Wow! I did not see that coming.”

So we shook up the industry a bit last week, but with the goal of crafting a first-rate portable stimulus standard as quickly and efficiently as possible. The high level of interest throughout DVCon India was more evidence that the time has come for graph-based and software-driven verification to become mainstream technology. I came back from the show energized and excited. As always, please comment if you agree, disagree, or have any questions. Thanks for reading!

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Accellera, Breker, Cadence, DVCon India, EDA, functional verification, graph, graph-based, horizontal reuse, mentor, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, SystemVerilog, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP

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