Archive for September, 2015
Wednesday, September 23rd, 2015
Anyone who reads The Breker Trekker from time to time needs no convincing from me that verification is a huge challenge for today’s complex chips. Breker’s Trek family of products exists, along with dozens if not hundreds of other EDA products, specifically to address functional verification. There are more technologies, tools, platforms, libraries, and methodologies than any one verification engineer can possibly learn and use on a day-to-day basis.
Why this diversity of solutions? As I first observed in Electronic Engineering Times nearly a decade ago, there is no silver bullet for verification. The problem is both so broad and so deep that no single tool or technology will ever satisfy the need. It takes a mix of solutions, guided by methodologies, to have any chance of first-silicon success. Low-power verification is an area where this is especially true, and unfortunately there is no silver bullet to be found here either.
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Tags: 1801, Accellera, ARM, Breker, Common Power Format, CPF, DV, EDA, emulation, formal analysis, functional verification, graph, graph-based, mentor, portable stimulus, scenario model, simulation, SoC verification, standards, Synopsys, test generation, TrekSoC, TrekSoC-Si, Unified Power Format, UPF, use cases
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Wednesday, September 16th, 2015
Last week, we discussed the details of a noteworthy press release that we issued with Cadence and Mentor Graphics announcing a joint contribution to the Portable Stimulus Working Group (PSWG) of Accellera Systems Initiative. As we expected, this release stirred up a lot of interest in portable stimulus. The timing was perfect, both because of today’s deadline for contributions to the PSWG and because of last week’s DVCon India conference. I’d like to provide some updates on both activities.
First of all, the three companies did upload our joint contribution document to the PSWG internal Web site today in time for the deadline. Please note that, as per the rules for Accellera and most other standards groups, working documents are not available to the general public. If you’d like to see the contribution and follow the evolution of the standard, please consider joining the PSWG. If your company is not yet a member of Accellera, then please alert your standards manager to the benefits of participation.
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Tags: Accellera, Breker, Cadence, DVCon India, EDA, functional verification, graph, graph-based, horizontal reuse, mentor, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, SystemVerilog, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Tuesday, September 8th, 2015
This morning, Breker issued a press release with Cadence and Mentor Graphics announcing a joint contribution to the Portable Stimulus Working Group (PSWG) of Accellera Systems Initiative. We expect that this news may be surprising to much of the EDA world, so we’d like to take today’s post on The Breker Trekker to fill in some background and offer you the opportunity to ask questions. Please note that we are speaking only for Breker in this post although we doubtless share many opinions with our co-contributors.
Let’s start with a quick summary of how Accellera works so that all readers understand the context for this major contribution. The portable stimulus effort started with a Proposed Working Group last year that assessed the interest in a standard and defined a set of more than 100 requirements that such a standard would have to satisfy. Accellera approved the formation of the PSWG and we began meeting in March of this year. We have refined the requirements list and also developed a set of “use cases” showing the sort of real-world verification problems that a standard would have to address.
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Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, graph-based, horizontal reuse, IEEE, mentor, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, subsystem, SystemVerilog, test, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Wednesday, September 2nd, 2015
A month ago, our blog post on The Breker Trekker concerned life on the hardware-software frontier. We discussed the ever-shifting line between hardware and software and how we at Breker seem to be straddling that line as we generate embedded C/C++ test cases for hardware verification. Yesterday we published an article on the ongoing merger between the worlds of embedded systems and EDA. We made a number of observations about how the two industries are drawing closer together.
We didn’t talk about Breker in yesterday’s article, but today we’d like to connect these two threads and talk about how we are now straddling the increasingly fuzzy line between embedded and EDA verification. This is a topic we’ve discussed internally from time to time, and we have taken some steps into the embedded world by exhibiting at ARM TechCon and publishing articles in magazine and on sites geared toward embedded designers and programmers.
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Tags: Accellera, Breker, device driver, EDA, embedded systems, functional verification, graph, graph-based, hardware, hardware-dependent software, HdS, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, software, software-driven verification, test generator, use case
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