Industry Drivers for DVCon India

Many of our readers may recall that Breker aggressively promoted the inaugural DVCon India last year. We supported the show itself by sponsoring a booth in the exhibition and delivering three conference talks. It turned out, much to our delight, that that hottest topic at the show was portable stimulus. There was a great deal of interest in the newly formed Accellera Portable Stimulus Working Group (PSWG) and how Breker’s products provided a well-tested solution meeting all of the PSWG’s requirements.

The second DVCon India is less than a month away, on September 10-11 at Leela Palace in Bangalore. I have every expectation that portable stimulus will be a major theme again. We’re also very busy promoting the event to ensure its success, especially since I am co-chair of the Promotions Committee. I will be covering the details of the sessions and our own participation in next week’s blog post. For today, I’d like to focus on some of the industry drivers that are influencing the interest of potential attendees and the selection of content for the technical program.

The ideas discussed here arose from preparation for a DVCon India newsletter and I’d like to credit Steering Committee General Chair Gaurav Jalan and Promotions Chair Prasanna Kesavan for contributing their thoughts to the discussion. As was the case last year, there are two tracks in the technical program: Design and Verification (DV) and Electronic System Level (ESL). The industry drivers for the DV track will look familiar to our readers, since many of these same trends have driven Breker and the evolution of our products.

The root for industry change is that the Universal Verification Methodology (UVM) has been very successful for IP development and some SoC projects, but verification teams have hit a wall in simulation. In fact, some teams perform very little simulation of the complete design, relying on hardware platforms such as in-circuit emulation (ICE) or FPGA prototypes. In addition to this move to hardware earlier in the project, two other trends are clear. The first is reliance on static methods such as formal analysis and advanced lint tools rather than simulation to find a wide class of design bugs. The second is the emergence of portable stimulus and software-driven verification.

Specific topics within the scope of the DVCon India DV track include:

• Multi-language and other extensions to the UVM
• Management of verification process, resources, and metrics
• Formal techniques, assertion automation/synthesis, and static verification
• Software-driven verification using C/C++ embedded test cases
• Debug automation, including identification of error sources
• DV extensions to handle verification of analog/mixed-signal (AMS) designs

The key driver for the ESL track is that systems and SoCs are growing ever larger and more complex. As noted above, traditional simulation testbenches running RTL have reached their limits of speed and capacity. Many SoC teams now focus on higher-level representations of the design, typically using SystemC models. Two key aspects of ESL-based development are driving industry innovation. The first is the use of efficient virtual platforms to simulate the high-level models for verification and for early assessment of performance and power consumption. The second is high-level synthesis to use the SystemC models as the golden design source and to generate RTL from them.

Specific topics within the scope of the DVCon India ESL track include:

• Transaction-level modeling of systems and SoCs
• Verification techniques using SystemC-UVM or other C/C++ testbenches
• High-level synthesis techniques to reduce power and increase performance
• Hardware-software co-development and co-verification
• Links between ESL and embedded systems software
• ESL extensions to handle modeling and verification of analog/mixed-signal (AMS) designs

The single biggest driver for the semiconductor industry as a whole has been the shift from industrial computation to consumer electronics. This transformation will continue with automotive electronics, wearables, and other Internet-of-things (IoT) applications. Low-power design techniques and power management will continue to be a key area of focus. Security and privacy become more important every day given the sensitive nature of data available from IoT devices. New standards for reliable design and verification are likely to emerge, and EDA tools must ensure conformance. These new techniques and standards will span multiple areas of SoC development, including:

• Performance and power management techniques across the entire development cycle
• Design and verification methodologies for privacy and security of IoT devices
• Compliance- and requirements-driven verification, including the DO-254 standard
• Emerging standards and new requirements for advanced automotive applications

Clearly there is a lot happening in the semiconductor and EDA industries right now. Many changes are in process and DVCon India will have a wide variety of keynotes, invited talks, technical papers, panels, and other sessions to address these changes. Please tune in to The Breker Trekker next week for more details on the program.

The truth is out there … sometimes it’s in a blog.

Tom A.

Tags: Accellera, Breker, dvcon, DVCon India, EDA, functional verification, graph, graph-based, mentor, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, software-driven verification, test generator, Universal Verification Methodology, use case, uvm, VIP

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