Archive for August, 2015
Tuesday, August 25th, 2015
For the most part, the terms “verification” and “validation” are used interchangeably in the electronics industry. However, there are many who argue that these are distinct activities in the development of SoC s and systems, performed at different times in the schedule and usually by different groups of engineers. We refer to ourselves as “The SoC Verification Company” and this is a deliberate choice we made. So we thought that it would be useful to define the two terms as we see them and talk about the similarities and differences.
This post was inspired by an article from 2010 that our CFO and co-founder Maheen Hamid discovered recently. It opens with the “usual definitions” as follows:
- “Validation: Are we building the right system?”
- “Verification: Are we building the system right?”
This seems like a good place to start the discussion.
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Tags: Breker, EDA, formal analysis, functional verification, graph, graph-based, portable stimulus, scenario model, simulation, SoC verification, software-driven verification, static analysis, test generator, Universal Verification Methodology, uvm, validation, VIP
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Thursday, August 20th, 2015
Last week we discussed some of the drivers in the electronics industry influencing the program for the upcoming DVCon India, September 10-11 in Bangalore. The Technical Program Committee has completed its arduous task of selecting among many worthy proposals for sessions and has posted a near-final program. Today we’d like to highlight some of the most interesting aspects of the packed two days, focusing on sessions that we believe will be a particular draw for those who follow Breker and SoC verification.
There are four conference-wide keynote speeches, from Atul Bhatia (formerly of nSys), Harry Foster of Mentor, Manoj Gandhi of Synopsys, and Vinay Shenoy of Infineon. They will set the tone for the event by discussing the high-level challenges in designing and verifying leading-age semiconductor devices. Nick Heaton of Cadence will keynote the Design and Verification Track (DV) while Pankaj Singh of Infineon and Dr. Sacha Loitz of Continental will give invited talks in the Electronic System Level (ESL) track.
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Tags: Accellera, Breker, CVC, dvcon, DVCon India, EDA, functional verification, graph, graph-based, IBM, mentor, portable stimulus, PSWG, scenario model, simulation, SoC verification, software-driven verification, test generator, Universal Verification Methodology, uvm, veriflabs, VIP
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Wednesday, August 12th, 2015
Many of our readers may recall that Breker aggressively promoted the inaugural DVCon India last year. We supported the show itself by sponsoring a booth in the exhibition and delivering three conference talks. It turned out, much to our delight, that that hottest topic at the show was portable stimulus. There was a great deal of interest in the newly formed Accellera Portable Stimulus Working Group (PSWG) and how Breker’s products provided a well-tested solution meeting all of the PSWG’s requirements.
The second DVCon India is less than a month away, on September 10-11 at Leela Palace in Bangalore. I have every expectation that portable stimulus will be a major theme again. We’re also very busy promoting the event to ensure its success, especially since I am co-chair of the Promotions Committee. I will be covering the details of the sessions and our own participation in next week’s blog post. For today, I’d like to focus on some of the industry drivers that are influencing the interest of potential attendees and the selection of content for the technical program.
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Tags: Accellera, Breker, dvcon, DVCon India, EDA, functional verification, graph, graph-based, mentor, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, software-driven verification, test generator, Universal Verification Methodology, use case, uvm, VIP
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Wednesday, August 5th, 2015
In last week’s post, we spent quite a bit of time talking about the concept of a (realistic) use case that reflected how actual users will eventually manipulate the design being verified. Our focus was on Breker’s graph-based scenario models and how they can easily and concisely capture such use cases. We did some research on the term “use case” and found that it seems to be more common in software design and verification than in hardware verification. That caused us to think about how we at Breker seem to be living on the hardware-software frontier.
It’s not uncommon for hardware designers and software engineers to borrow ideas from each other. Code coverage, for example, was well established in software before it was adopted for hardware design and verification languages. With the move from gates to RTL, hardware became just another form of code and therefore more amenable to software techniques. This is just one example showing that the boundary between hardware and software is fuzzy and changing over time.
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Tags: Accellera, Breker, device driver, EDA, functional verification, graph, graph-based, hardware, hardware-dependent software, HdS, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, software, test generator, use case
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