A First Look at the Program for the 52nd DAC

Over the nearly two years we’ve been blogging on The Breker Trekker, some of the most popular posts have been our previews of, and reports from, the annual Design Automation Conference (DAC). The show remains a must-attend event for all EDA vendors and users. One of the key ingredients for its success it that it is really two events in one: a strong technical conference with peer-reviewed papers and a formal Proceedings, plus a busy exhibition floor with vendor booths and suites for prospecting, demos, and update meetings with current customers.

For me personally, it’s almost impossible to imagine not going to DAC. I’ve attended every show since 1988 for at least one of its days, and in many cases for the entire run. DAC stories might be a fun topic for a future post but today I’m going to look ahead rather than back. The technical program for the 52nd DAC was unveiled a few days ago and I’ve been scrolling through the pages on the Web site to see who’s speaking and what topics are hot. This post offers some initial thoughts on sessions likely to be of interest to you, our readers, and a few predictions on what will emerge as the major themes for 2015.

One change that the DAC committees have made over the past few years is to focus more on the end products that EDA enables. This is reflected in the keynotes, which include none of the EDA industry’s leaders. Experts from Google, General Motors, DELPHI Automotive, Intel, and other companies have the stage. Topics include medical electronics, wearable technology, smart automobiles, and Moore’s Law enabling these breakthroughs. Not surprisingly, the Internet of Things (IoT) is featured in numerous talks and special sessions, some of these held in the DAC Pavilion on the exhibit floor so a full-conference pass is not needed to attend.

I suspect that verification will figure into a number of these talks, especially those on security. The very thought of someone hacking into a self-driving car or an implanted medical device is chilling. It will be critical that the hardware, software, and combined system be bulletproof as verified by both today’s techniques and new innovations. I certainly believe that Breker’s SoC verification approach will be a key part of this solution. In the main technical program, I count eight sessions (of 75 total) with “verification” in the titles. These are, in chronological order:

• “IP Verification” on Tuesday, 10:30am – 11:30am : Intel, Cisco, Freescale, and TI on IP verification, SoC verification, DDR4, and verification sign-off
• “Innovative Front-End Design and Validation at System Level” on Tuesday, 1:30pm – 3:00pm : Huawei, Synopsys, IBM, Qualcomm, and STMicro on SoC verification, UVM, IP-XCAT, SystemC, and more
• “Verification from Transactions to Transistors” on Tuesday, 4:30pm – 6:00pm : Mentor and several universities on a verification survey, symbolic simulation, sequential equivalence checking, clock gating, etc.
• “The Expanding World of System Verification” on Wednesday, 1:30pm – 3:00pm : TI, Qualcomm, and NVIDIA on security verification, high-speed serial interfaces, and software testing
• “SystemVerilog Verification: Hardcore SystemVerilog for Class-Based Verification” on Thursday, 10:15am – 1:15pm : Doulos training session on the object-oriented programming constructs of SystemVerilog
  
• “Automotive Verification and Validation Challenges” on Thursday, 10:30am – 12:00pm : Toyota, Infineon, and Computer Research Institute of Montreal on control models, SoC firmware, and model-based testing
• “Validation, Validation, and Validation: The 1-2-3 of Secure SoC” on Thursday, 1:0pm – 3:00pm : TI, University of Central Florida, and Intel on security architecture, formal security verification, and post-silicon validation
• “SystemVerilog Verification: Easier UVM” on Thursday, 2:15pm – 5:15pm : Duolos training session on the Accellera Universal Verification Methodology (UVM) standard for SystemVerilog

I have to say that I am very impressed with this list of sessions, speakers, and topics. Verification is clearly another key focus for DAC this year. By Thursday, I’m usually exhausted after several days setting up the booth and three days of exhibits. This year I’m going to be very tempted to stay through the end of the day to attend these talks. I’d like to bring your attention specifically to the IBM talk “Walking the Graph: A Holistic Approach to Graph-Based Verification for Logic with Sparse State Space” in the second session listed above. This group is a long-time Breker customer and a strong industry advocate for using our graph-based scenario models.

We’ll be talking more about DAC as the show gets closer, including our own theme for the exhibition and what we’ll be demonstrating in our booth. This year’s event will be held in San Francisco’s Moscone Center June 7-11. Please share any questions or comments about DAC in the comments section below. We hope to see you there!

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Accellera, Breker, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, Universal Verification Methodology, uvm, VIP

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