If Your Chip Is Not a Cache-Coherent SoC, It Soon Will Be

Yes, we know that the title of this week’s post sounds a lot like two previous posts. We wanted to link together the two threads from those posts into a single message that we believe reflects what is happening right now in the world of complex chips. This is a short summary in line with the short week due to the Thanksgiving holiday here in the United States. The line of argument is straightforward:

• Large chips are adding embedded processors to implement complex functionality while retaining flexibility
• Single-processor chips are adding multiprocessor clusters to get better performance at a given process node
• Multiprocessor chips are using shared memory for effective data transfer and interprocess communication
• Neighbor-connected processor arrays are moving to shared memory to reduce cross-chip data latency
• Multiprocessor designs are adding caches to reduce memory access time and bypass memory bottlenecks
• Multiprocessors with caches require coherency in order to ensure that the right data is always accessed

While most of these statements are not universally true, they reflect a significant sea change that we see every day when discussing current and future projects with our customers.

In some ways, most large chips are starting to look like the SoCs for smartphone and tablets that we targeted when we introduced TrekSoC three years ago. We’ve added the following diagram to many of our presentations, and have received general acceptance from engineers in various industries.

This diagram succinctly captures our observation that simple bus-based SoCs, non-SoCs such as networking chips, and arrays of processors are all moving toward multi-processor, shared-memory, multi-level-cache-coherent SoCs. It is precisely this industry transition that is driving intense interest in TrekSoC, TrekSoC-Si, and our Coherency TrekApp. As this transition happens, cache coherency moves from the domain of the CPU architect to become a problem for everyone designing and verifying SoCs.

We’ve made some fairly bold claims here, but they do reflect what are seeing and hearing. If your world is changing in this way, then we have the solutions for cache coherency pre-silicon verification and post-silicon validation available today. If your view of the chip and SoC industry does not match ours, please submit a comment so that we can get a lively debate going. Thanks, and if you have time off this week please enjoy it.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Breker, cache, Carbon, coherency, CPAK, DV, functional verification, IoT, IP, portable stimulus, SoC, SoC verification, TrekApp, TrekSoC, TrekSoC-Si, uvm, VIP

This entry was posted on Tuesday, November 25th, 2014 at 6:31 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.