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Jean-Marie Brunet
Jean-Marie Brunet
Jean-Marie Brunet is the Vice President and General Manager of Hardware Assisted Verification at Siemens EDA. He has served for over 25 years in management roles in marketing, application engineering, product management and product engineering roles in the EDA industry, and has held IC design and … More »

Facing a New Age of IC Design Challenges Part 1

May 16th, 2024 by Jean-Marie Brunet

In an industry accustomed to incremental change, Veloce CS is a departure because it is a complete three-in-one system, a development that Ron Wilson, a longtime technology editor, explores with Brunet in this 2-part blog.

Wilson: How do you describe the Veloce CS system?

Brunet: The Veloce CS system is architected for congruency, speed and modularity and supports design sizes from 40-million gates to designs integrating more than 40+ billion gates. It executes full system workloads with elevated visibility and congruency, enabling teams to select the right tool for a task’s unique requirements for faster time to project completion and decreased cost per verification cycle.

Wilson: Why now?

Veloce CS SystemBrunet: We recognized the discontinuity triggered by the convergence of AI-related hardware, software defined product, new process technology and the emergence of chiplet-based systems. We responded by developing three economical, scalable systems that directly address the needs of design teams. Our goal with the Veloce CS system is to be the instrument to create the next-generation advanced ICs and multi-die modules bringing new levels of productivity to design teams and new levels design and schedule integrity. We envision a new value proposition for IC vendors, IP houses or systems developers who will transform these advanced IC designs into earnings growth.

Read the rest of Facing a New Age of IC Design Challenges Part 1

The Strategic Advantage in the Hardware-assisted Verification Segment

May 9th, 2024 by Jean-Marie Brunet

Welcome to the Siemen hardware-assisted verification blog. Technologies in this blog include software-based tools for architectural design and verification, focus-based applications, hardware emulation, and FPGA prototyping.

EDA is generally a software-centric product space. So why does a hardware-oriented vendor like Siemens have a strategic advantage when it comes to chip design and verification? Because we design and verify our own chip for the Veloce Strato CS emulator.

In addition, the Veloce hardware-assisted verification portfolio is expanding rapidly and has taken a primary role in the pre-silicon verification process. It is now an integrated system of software-based tools for architectural design and verification, focus-based applications, hardware emulation, and FPGA prototyping.

The Veloce portfolio is the perfect example of designing a chip targeted for a specific application through our hardware emulator known as Veloce. We design and verify Veloce’s Crystal chip and use the same tools we are offering customers. This makes us intimately familiar with their challenges because we are exposed to the same problems that they are, specifically how big chips get designed and verified to meet time-to-completion schedules.

Every new generation of our chip gets verified by our current hardware emulator generation, giving us insight into our customers’ challenges and credibility when we speak to them, as well as an insider’s understanding of the trends. Since we design complex devices, we know the verification trends because we’re going through them ourselves. It’s an important consideration for companies evaluating their HAV providers.

We see firsthand that verification has changed because the requirements have changed dynamically. It is no longer about making sure the chip is working. Other criteria are equally or more important now. It’s knowing what kind of verification is needed or validation may not be enough when building a chip that differentiates us. After all, our designers are no different than AI accelerator chip designers. Our designers make sure we have chips that are deliverable, whether it’s for our emulator or for a customer’s system.

In addition to chip complexity and size, things have changed. For us, it’s the importance of yield that directly impacts margins. Our designers continually refine our processes to improve yield and consume less power. If our chip, system or emulator is going to a data center, they need to consider that the data center charges by the power plug and not by how much space is being consumed. That means power is important and the reason our system is popular with chip designers and used to verify 15-billion chip designs and larger. Speed is important and our HAV runs their workload faster.

Hardware-assisted verification is an important market segment and growing tremendously because trends are accelerating and not slowing down. Intractable chip design complexity, size and performance challenges mean this segment will continue growing for the next five years and beyond.

To learn more read our latest white paper, Facing a new age of challenges in IC design

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