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Veloce proFPGA CS Changes the Game for Software Prototyping

Monday, September 9th, 2024

With the AMD VP1902 FPGA device boasting double the capacity, you unlock a whole new level of performance and cost-effectiveness.

Whether pushing the boundaries of SoC verification, validating complex IP blocks, or simulating massive software workloads, the Veloce proFPGA CS software prototyping platform, equipped with the VP1902 FPGA device, doubles the capacity and delivers verification success.

Performance. You can map more of your design onto a single chip. This means that fewer FPGA devices are needed overall, resulting in streamlined mapping and improved performance. The benefits extend beyond performance. With fewer FPGA devices required, the cost per gate for your prototyping platform plummets. That’s right – 50% lower cost per gate means significant savings for your budget. You can achieve more with less, maximizing the performance of your resources.

Consolidation: Mapping your design onto a single high-capacity FPGA simplifies the setup and configuration process. No more juggling multiple devices or dealing with complex interconnectivity.

Simplifying setup and configuration means faster and more efficient prototype bring-up, allowing you to accelerate your development cycle like never before. You have more opportunities to test different scenarios, catch potential corner case issues, and optimize the quality of your design.

To learn more, download the Veloce proFPGA CS factsheet or email Romain Petit romain.petit@siemens.com for details.

FPGA-Based Prototyping – from “Do-It-Yourself” to an Essential SoC Verification and System Validation Tool

Monday, August 26th, 2024

FPGA prototyping kitFPGA-based prototyping has always been something of an assembly-required construction kit. Consequently, getting to a functional and usable prototype took a lot of effort, time, and a ‘do it yourself’ attitude. Once up and running, however, the reward justified the effort by providing a fast pre-silicon verification platform, with frequencies often running at tens of megahertz and reducing verification workload runs from days to minutes.

Then chip designs exploded in complexity, software content increased exponentially, and the sheer amount of data going in and out of an SoC grew by orders of magnitude. And let’s not forget that design cycles shrank at the same time. FPGA-based prototype platforms, uniquely suited to address those challenges, have become essential to SoC verification and system validation.

As all this change was happening, prototyping evolved as well. Today it is no longer a construction kit, but a ready-to-use, comprehensive solution that delivers significant productivity gains.

You might ask, what are the primary attributes of this evolved FPGA-based prototyping platforms? Obviously, it’s hardware consisting of one or more FPGAs!

It’s also the software that takes the ASIC RTL and intelligently maps it into the collection of FPGAs.

It’s also a test environment that stimulates the design, often with live system interfaces like sensors, cameras, and ethernet traffic.

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Accelerating your simulation runs. Bridging the simulation and emulation gap using Veloce sim-accel methodology

Monday, August 12th, 2024

Welcome to the world of Siemens Hardware Assisted Verification (HAV) engines, a fast-paced verification ecosystem that synthesizes the design and a large part of the testbench and then maps it to the Veloce Hardware. This setup runs 1000 to 10000 times faster than a simulator.  Roughly, the same design that took days and weeks now runs in minutes. That’s incredible, isn’t it?   

 A verification environment typically has a design under test (DUT) surrounded by verification-driven constructs.   No synthesis tool can synthesize every supported keyword. Design engineers are always careful with limiting themselves to using synthesis-friendly constructs. Verification engineers are more fluid because they do not worry about synthesis. Emulators are no exception. They can synthesize the design, but the testbench runs on a host machine. The two communicate through interfaces or established standard protocols.  

 Now, such a system is like a relay race. The slowest player can significantly impact the overall performance. The obvious solution is to assign the shortest lap to the slowest player. Simulators are painfully slow in the relay race of Emulators and Simulators. How do we further reduce the time spent on simulators?    

 The Siemens Veloce team took a multi-pronged approach to provide a solution.   

First, Veloce provides a rich set of Veloce transactor libraries (VTLs) of standard protocols and soft memory models. These VTLs are emulation-ready, geared towards performance, and support plug-and-play. A user simply replaces the simulation Verification IP (VIP) with an equivalent Siemens VTL to migrate a large portion of the design. The VTLs cater to large industry segments such as networking, automotive, storage, video, mobile/smartphone, and 5G, to name a few.       

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Supercharge Your HAV Investment with Veloce ES (Enterprise Server) App

Monday, July 29th, 2024

In today’s fast-paced world of hardware design and verification, accelerating time-to-market and optimizing resources are paramount. Hardware-Assisted Verification (HAV) significantly reduces verification time, allowing hardware design teams to meet tight deadlines and bring products to market faster. Moreover, HAV enables thorough testing of intricate designs, uncovering potential issues early in the development cycle and ensuring product reliability. While HAV represents a significant investment and offers numerous benefits, managing multiple projects, diverse teams, and varying job priorities on a shared HAV platform can be overwhelming. Enter the Veloce Enterprise Server (ES) App – a revolutionary solution developed by Siemens EDA to streamline Veloce hardware resource management and transform the HAV landscape.

Understanding Hardware-Assisted Verification

Hardware-Assisted Verification (HAV) uses dedicated hardware to accelerate the verification process of semiconductor designs. This approach allows for faster execution of test cases compared to traditional software-based simulations, significantly speeding up the verification cycle. HAV is particularly beneficial for large and complex designs, where traditional simulation methods fall short in terms of speed and capacity. For more information on Siemens EDA HAV, see the article, “Siemens delivers next-generation, comprehensive hardware-assisted verification system”.

However, managing the efficient use of HAV resources, especially when dealing with multiple projects and teams, poses significant challenges. This is where the Veloce ES App comes into play.

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The Veloce Ecosystem: Applications Targeted to Solving End User Challenges

Monday, July 15th, 2024

In the rapidly evolving semiconductor and electronic design world, hardware-assisted verification (HAV) has become an indispensable part of the design process. The use of hardware platforms like emulators and FPGA-based prototyping systems to enhance the verification and validation process, ensure designs meet their specifications efficiently and effectively.  But what about the end users challenges and use cases What tools and technologies are available to help enable a more efficient verification/validation environment or help with verification closure?   What about teams who are tasked with HW/SW Co-verification tasks? Do they have the necessary tools and applications to get their job done?    I think asking these critical questions and examining the use cases is important to providing a comprehensive solution that addresses the verification and validation team’s needs.   To help understand how Siemens EDA is solving this challenge, let us delve into some key use cases of HAV, enabled by Veloce Apps 

Software development, debug, and validation
It is well known that Hardware-assisted verification plays a crucial role in software development, particularly in the initial stages of chip design. By using emulators, developers often run full workloads/software on hardware models, allowing them to identify and fix issues before the physical hardware is available.  By providing full reference designs that operate stand-alone, or in a hybrid execution model with HAV platforms, one significantly accelerates the development cycle and reduces the risk of costly post-silicon bugs because system-level workloads were not run.

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