Author: Matthew Hogan

A shift-left strategy to tackle the complexities of power domain leakage in IC design

Managing leakage power is a critical challenge for IC designers, as it can profoundly impact a device’s power, performance, area (PPA) and overall reliability. Leakage can manifest in various ways, from analog gate leakage causing high current drain to digital gate leakage leading to power management and reliability issues. Even subtle circuit changes can introduce leakage problems that compromise the final product. Traditionally, designers have left verification of these leakage issues until later design stages, resulting in costly rework. However, a shift-left approach that integrates leakage and reliability analysis into the pre-layout phase can help identify and address potential problems early on. By leveraging advanced EDA tools that take a holistic view of the circuit, designers can get ahead of leakage challenges and ensure their ICs meet the highest standards of quality and reliability.

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Almost as long as FPGAs have been around, they have been used to prototype ASICs, SoCs, and IPs. While initially, the only option for users was to build their own prototyping board, that quickly changed with many commercial prototyping boards becoming available from vendors large and small. Ever since, the large question for users has been, should I develop and build or buy my boards?

Now, consider the pros and cons of this “build vs. buy” debate. But before that, probably the first question to ask yourself is what do you want the FPGA-based prototype to do? Having that answer allows you to consider the right priorities and trade-offs inherent in the decision to build or not to build a board.  Let’s assume you buy rather than build, which commercial solution should you purchase? Key questions to ask yourself here are:

• What is the primary use mode, HW (RTL) verification or SW validation?
• How many FPGAs per board/system are needed to handle my design (e.g. single vs. multi-FPGA)?
• How many boards will I need?
• What physical at-speed interfaces do I need?
• What is the minimum performance the FPGA board must run at?
• What is my budget?

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As integrated circuit (IC) designs continue to scale, the demand for efficient power management, optimized performance and reliable physical layout modification grows more critical. Meeting power, performance, and area (PPA) targets is essential for effective IC operation at advanced process nodes. However, design and verification engineers face challenges in addressing issues like IR drop and electromigration (EM) early in the design process without compromising PPA objectives.

This is where a shift-left approach to power grid optimization can make a significant difference. By making design-stage layout modifications, designers can proactively tackle power management issues, enhancing reliability and PPA metrics. This strategy not only benefits engineering teams but also delivers substantial business advantages by reducing rework, lowering costs and accelerating time to market.

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A trend sweeping through chip design is changing the traditional markets for CPUs and GPUs. Along the way, it is accelerating the number of design starts for artificial intelligence (AI) and building chips known as custom accelerators.  

The custom accelerator trend is driven by system companies becoming semiconductor companies not relying on other companies to build their chips. They do most of the chip design in house to control the ecosystem, roadmaps, and time to market, adopting a different perspective. A good example is Apple. It’s designing its own iPhone and Mac chips now and they are not the end product. Their end product is a system that includes peripherals and software. 

In today’s landscape, both semiconductor and system companies are racing to make announcements about their own custom accelerators in a vibrant and growing market segment. A custom accelerator is an ASIC, or a chip dedicated to a specific function. It is not a generic CPU or GPU. Nor is it an application serving a broad market. Instead, it is a well-defined, custom-designed accelerator for a specific AI or machine learning (ML) function. 

A company uses AI and ML to design its chips and they are not designed by hardware engineers. Because everything starts with a software driver, software defines the product. This new type of user is not taking the derivative of a whole design for targeted chips to address a specific market or application. In this design flow, hardware design is started only after the system specification is defined. 

The number of companies making AI or ML chips are generating requirements for loads of verification of big systems because these chips are large and need to run massive workloads and software. The growth is in many areas, not just one. Add hyperscalers as another category not relying on traditional semiconductor companies. All are making their own chips where the size of the workload they run are perfect fits for an emulation and prototyping platform.  

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