You may remember the Oski Technology Live Verification Challenge in 2012, where during the 72 hours of DAC, Oski verification engineer Chirag Agarwal formally verified a well-simulated design from NVIDIA, sight unseen, live and on camera, and found 4 corner case bugs. The challenge results exceeded everyone’s expectations, and inspired other companies to do more with formal in their verification flow. See the Live Oski Verification Challenge, and a blog recap and six-minute video, here.
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Decoding Formal
Posts Tagged ‘formal sign-off’
Preparing for Another Challenge at DAC: Break the Testbench!
Monday, May 18th, 2015The Impact of Great Teachers
Friday, May 1st, 2015My daughter has been learning violin for the last 5 years with a wonderful Suzuki teacher. She emphasizes proper posture, beautiful tone and a good work ethic. This has built a solid foundation for my daughter to venture into learning other instruments. Last fall my daughter started playing flute for her school band, and viola at Young String Ensemble, the youngest division of Portland Youth Philharmonic, founded in 1929 as the first youth orchestra in the United States.
To help her prepare for the upcoming audition for the more advanced Portland Youth Conservatory Orchestra, we decided she would take some viola lessons with the Oregon Symphony Principal Violist. We were totally blown away after just one lesson.
“Shift Left” with Formal Technology
Wednesday, April 1st, 2015“Shift Left” has become a hot phrase after Aart’s keynote speech at DVCon2015 where he talked about how shifting left in schedule resulted from 10x productivity gain in design, IP, verification and software can spur on 100x opportunities in applications across all fields. He suggested many of these technological advances have the potential of changing what mankind is all about.
Static and formal techniques were mentioned as one of the mechanisms that increase productivity and contribute to shift left in the verification schedule. There are several reasons why formal technology is a key driver for the left shift.
Making the Case to Executives for Formal Verification
Tuesday, February 3rd, 2015Last year, after my presentation to a customer in Asia, the verification manager said, “You should give this talk to our senior executives, so they understand the benefits of formal.”
It was said in a lighthearted manner, but in reality it rang true. Design and verification engineers and their managers understand the value of formal. However in order to request funding to promote formal adoption, they still need to make a case to senior executives as to the value of formal. They need compelling arguments, speaking at a strategic level as to why it is critically important and urgent for the company to adopt formal. The list of concerns for senior executives, is long:
- Are we staying ahead of competition?
- Do our customers have any issues with our products?
- Can we deliver our products on schedule and with profit margin?
Funding will become easier, if they understand how formal can address their primary concerns.
To stay ahead of competition not only requires innovative ideas, but also a sharpened toolkit. Semiconductor companies large and small are actively investing in formal adoption so that they have the best verification flow with the most advanced tools and methodologies. There aren’t many formal experts who can do End-to-End formal in the industry. Many companies are paying top dollar to attract formal verification engineers or outsource formal verification tasks for critical projects to the Oski Technology. So if your company doesn’t use formal verification, then this is an easy case to make, in order to catch up with competition.
A post-silicon bug is a nightmare to senior executives. It signifies poor quality, delayed schedule and wasted money. No matter how complex the bug might be at the system level, it resides in one of the design blocks and could have been caught earlier. Using End-to-End formal to achieve sign-off is a sure way to catch corner case bugs early in the flow so as to minimize, or even avoid, post-silicon bugs. So if senior executives are concerned about customer issues with products, the best solution is to incorporate formal in the early stage, for sign-off.
Time is money. Delayed project schedule means extra engineering time and lost potential market opportunity. Formal can reduce project schedule as in the Oski Cisco case study, published at DAC 2011. At the very least with formal, once a property is proven, verification is done. Unlike simulation where reaching the last 20% of coverage closure could take 80% of the time, so there is never a real sense of being complete as it is impossible to simulate all input vectors.
So if adding formal to the flow helps you keep up or stay ahead of competition, avoid post silicon bugs and keep your project schedule in check, it has a big impact for the company. This should make a strong case to senior execs that formal is something they should hear about – and sponsor – today.
Rob Kurshan, early pioneer and expert in formal verification, speculates here on the future of formal verification in a video interview at a past meeting for the Decoding Formal Club, a forum hosted by Oski Technology for formal enthusiasts, pioneers, leaders and colleagues who work to promote the sharing of ideas and the advancement of formal technology. On February 9 Synopsys is sponsoring the next Decoding Formal Club Meeting about constraints, liveness vs. safety, formal at ARM (and a Klein bottle). Space is limited and pre-registration is required. Sign up here.
“What if” All Design and Verification Engineers Used Formal?
Monday, November 10th, 2014What if all design and verification engineers used formal? What if formal tools become smart enough to do the abstractions? What if formal tools had infinite capacity? These and other questions were proposed by attendees on the event survey for this quarter’s Decoding Formal Club event on October 23, 2014 at the Computer History Museum in Mountain View, CA. (more…)
Formal Verification, by Everyone and for Everyone
Thursday, September 18th, 2014You might still be skeptical of the idea that formal verification can be used by everyone. After all, there is a deep-rooted perception in the industry that formal verification is for the elite few formal experts with Ph.Ds.
This might have been true in the early days of formal technology. The formal tools’ capacity was limited and the use model was not mature. So the aid of someone who actually understood the algorithms “under the hood” was important to help the tool solve the tasks at hand.
However, things have changed dramatically in the last decade. (more…)
Formal Training in High Demand
Thursday, June 19th, 2014This year at DAC, a question asked repeatedly got our attention: Do you offer advanced formal training program?
While we are not surprised by the request itself, the number, size, type and location of companies that asked about this was surprising. It included a wide spectrum of companies, from the U.S., Japan, Korea, China, along with large companies with established formal teams as well as small start-ups with no formal experience. Even EDA vendors asked if we could do training for them. (more…)
How Long Does It Take to Formally Verify This Design?
Friday, June 13th, 2014This year at DAC, we asked attendees to participate in a guessing game – make an educated guess about how long it takes to formally verify a design based on the given design description and statistics.
How Long Does it Take to Formally Verify This Design?
Here is a recap of the information provided to participants:
Design Description
Reorder IP packets that can arrive out of order and dequeue them in order; when an exception occurs, the design flushes the IP packets for which exceptions has occurred. Support 36 different inputs that can send the data for one or more ports. Another interface provides dequeue requests for different ports. Design supports 48 different ports.
Design Interface
Packets arrive with valid signal; a request/grant mechanism for handling requests from 36 different sources; All 36 inputs are independent and can arrive concurrently; All 48 ports can be dequeued in parallel using another request/grant mechanism.
Design Micro-architecture Details
Supports enqueue and dequeue for IP packets for 362 different input and 48 different ports respectively; 48 different queues used to store IP packets for different ports; A round robin arbiter resolves contention between enqueue requests from different sources for the same port at the same cycle. (more…)
Cooley’s Report: Only Half The Story?
Friday, May 23rd, 2014Every year John Cooley publishes a DAC “must-see” list – a veritable treasure map of good stories. While this list has served DAC attendees in the past, in recent years it has continued to miss an important segment of the ecosystem: the growing number of service providers.
Oski Technology is one such service provider. In fact Oski is the only service provider in the formal verification space, and plays an important role in promoting formal adoption in the industry. Formal can improve verification efficiency and productivity, lead to reduced project cost and shorten time-to-market. Since 2005 we have partnered with many leading semiconductor companies to tape out mission-critical designs and build up their internal formal expertise. (more…)
Oski Receives DVCon “Honorable Mention” for Best Paper on Bounded Proofs
Thursday, March 20th, 2014DVCon 2014 was a terrific show for Oski Technology. Not only were we proud to receive an “Honorable Mention” for (2nd) Best Paper at DVCon “Sign-off with Bounded Formal Verification Proofs”, we had the opportunity to have many meaningful conversations with existing customers and others new to formal verification and eager to learn more about what is possible with formal verification. Our DVCon “Sign-off” paper is available on the Oski Technology Web site. See our DVCon 2014 video here.
