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 Decoding Formal

Posts Tagged ‘DVCon’

The ABCs of Winning at the 2017 Hardware Model Checking Competition

Wednesday, March 7th, 2018

Every year for the last nine years teams of researchers and software developers have come together to compete in the Hardware Model Checking Competition (HWMCC). This contest pits some of the brightest minds in design and verification against each other along with the solvers they have developed. Each team has worked tirelessly over the course of the past year to develop their solver and get it ready for the big day.


Vigyan Singhal (center), President and CEO of Oski, presenting the award at the HWMCC Award Ceremony to ABC member, Yen-Sheng Ho (far right). : Armin Biere, organizer of the HWMCC Competition shown far left.

The competition boasts benchmarks in three categories including single safety property track, liveness property track, and deep bound track of which Oski is a sponsor. The benchmarks come from a combination of missed benchmarks by competitors in previous years’ competitions and from leading companies in industry like Oski that directly relate to the most complex issues of the day. It is this combination of benchmarks that pushes these teams to develop solvers so robust in nature that after the competition many of the attributes are adopted by the large system houses to help tackle industrial strength challenges.

Of all the teams competing in the HWMCC, there is only one team that has consistently taken first place in the single safety property track since they entered the competition in 2008. This year however, they not only won the single safety property track, but also ran away with first place in the liveness track, and the deep bound track. No other team in the competition’s history has ever done that. The team that achieved this is the ABC team from the University of California at Berkeley. Recently, I got a chance to sit down with them to find out their secret to such unprecedented success.

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Oski Receives DVCon “Honorable Mention” for Best Paper on Bounded Proofs

Thursday, March 20th, 2014

DVCon 2014 was a terrific show for Oski Technology. Not only were we proud to receive an “Honorable Mention” for (2nd) Best Paper at DVCon “Sign-off with Bounded Formal Verification Proofs”, we had the opportunity to have many meaningful conversations with existing customers and others new to formal verification and eager to learn more about what is possible with formal verification. Our DVCon “Sign-off” paper is available on the Oski Technology Web site. See our DVCon 2014 video here.

DVCon 2014 Oski Technology, Vigyan Singhal

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Countdown to DVCON 2014

Friday, February 28th, 2014

The countdown to DVCON 2014 has begun! With more exhibitors and attendees than ever before, new programs and technical sessions, longer exhibit hours, DVCON 2014 is shaping up to be another outstanding event for the industry.

At Oski Technology, we are excited to offer many opportunities to connect with verification experts in the industry at DVCON – share ideas, discuss problems and solutions related to formal technology and formal sign-off methodology.

• Monday March 3rd 5:00 – 7:00pm, Oski will join the inaugural DVCON Booth Crawl and offer healthy stacks – nuts, veggie sticks and wine, while we enjoy great conversations. Come and chat at the Oski booth #305. (more…)

Verification Management from a Formal Perspective

Tuesday, February 18th, 2014

Recently, Gabe Moretti, contributing editor to Chip Design, wrote a lengthy article for Systems Design Engineering addressing an important topic, “Verification Management.” It included comments from Atrenta, Breker Verification Systems, Jasper Design Automation, Mentor Graphics, OneSpin Solutions, Oski Technology and Sonics on a series of questions from Gabe on how to manage today’s complex and time-consuming verification process.

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Oski Innovation Enables Formal Sign-Off in 2013

Thursday, December 19th, 2013

A busy year is drawing to a close for Oski Technology. Reflecting back on this year we are proud of what we have accomplished for our valued customers. Oski Formal Sign-off Methodology, incorporating End-to-End checkers, Abstraction Models and formal coverage – this is the boldest application of formal technology for RTL functional verification.

Gone are the days when formal can only be used to compliment simulation on a given block. Oski Formal Sign-off Methodology and formal verification can replace block-level simulation for suitable designs to improve overall verification coverage, efficiency and productivity. The logic is simple – control and data transport types of blocks and designs with complex corner scenarios are better suited to be verified with formal than simulation. We have applied such methodology to tapeout many of our customers’ mission-critical projects and at the same time develop formal expertise in our customer base.

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ClioSoft at DAC
Altair
TrueCircuits: IoTPLL



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