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Posts Tagged ‘SAR architecture’

S3 Tutorial: SAR ADC, Node2Node, IP Integration, Analog with a ‘ue’

Thursday, April 10th, 2014

 

Several weeks ago, I had a chance to speak by phone with the folks of S3, a multinational IP vendor and engineering company headquartered in Dublin, Ireland. Darren Hobbs, Director of Product Strategy for the Silicon Business Unit, was on the call, as was Dermot Barry, Vice President of the Silicon Business Unit.

Our conversation centered on two topics: a new ADC just released by S3, and my hypothetical design project, the Dick Tracy keychain. It was morning in California when we spoke, but closing in on dinner time in Ireland. Hobbs and Barry were patient with my questions, nonetheless.

Per Hobbs, “We want to talk today about our latest product, a high-speed ADC and one of the most efficient [in the marketplace]. This announcement has produced a lot of headlines, but we want to drill into what it all really means. The specs we are using here is performance per milliwatt. We harp on that, because it’s really critical today. Typically, what’s said with a launch like this is that it [processes so many bits at a particular speed], but that doesn’t really indicate the performance of an ADC.

“What we’re doing here is putting our necks on the line by saying instead what our efficiency is – a very, very small ADC when manufactured at 40 nanometers, just .09 square millimeters, and only consuming 6 milliwatts of power. It’s efficient in the order of 31 femtojoules [10-15 joules], which means for handsets that use 802.11ac, you get very high energy efficiency.”

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