The following article is by Ms.Linh Hong, vice president of marketing at Kilopass Technology, Santa Clara, CA, and first appeared in the Jan. 9 issue of EDA Weekly.
Starting its second decade in business under current CEO Charlie Cheng, Kilopass Technology Inc. continues its successful growth driven by two major movements. The first comprises market forces where consumers are demanding greater functionality from their mobile smart devices beyond audio and video to include environmental data that will eventually provide life care for the consumer. The second involves technology forces that continue to deliver more transistors per silicon area for each new semiconductor process generation, now at 28nm going to 20nm.
The widespread adoption of Kilopass’ unique standard logic CMOS anti-fuse, one-time programmable (OTP), non-volatile memory (NVM) intellectual property (IP) is reflected in the growing number of Kilopass foundry and IDM partners. Among foundries signing new agreements are UMC, SMIC, GLOBALFOUNDRIES, Dongbu and TowerJazz, that join long-standing Kilopass partner TSMC, the first to offer Kilopass IP at 28nm. The key to success for an IP company is silicon enablement and Kilopass IP is available on process nodes from 180nm down to 28nm at its major foundry partners to provide solutions to customers across many markets. Among major Integrated Device Manufacturers (IDMs) inking deals with Kilopass are the major suppliers of image sensors, display drivers, and gaming chips.
To understand how this successful start-up is being driven by evolutionary technical and market forces, an explanation of the company’s patented anti-fuse NVM IP and how it compares with alternative NVM solutions is the place to begin. Next, a description of how this anti-fuse NVM IP has symbiotically evolved with the steady progression of each new generation of standard logic CMOS processes, currently at 28nm and moving to 20nm and beyond, is in order. Finally, a discussion of how the anti-fuse NVM IP uniquely serves the four high-volume applications where it is being incorporated will detail how market forces are driving the company’s ongoing success.
The January Cosmic Rays newsletter from Cosmic Circuits detailed the issues for creating custom ASICs for sensor front ends. The article is shown here:
Custom ASICs are often deployed in sensor read-out electronics. These read-out systems tend to be unique and require the custom ASIC to
realize the unique functions at the power dissipation suitable for the system,
reduce cost and
protect intellectual property.
This article walks through the key elements of a custom solution for a Sensor Front End.
Successful Sensor Front Ends usually consist of the following key elements in realizing a complete solution
Robust architectural definition
Sensor interface electronics – often a preamplifier or instrumentation amplifier
ADC
Sensor excitation circuits
Calibration and Production support
Architecting the solution
Some of the key architectural decisions need to be made early in the architecture phase – these include AC or DC excitation of the sensor, , observation time of the sensor signal, voltage definition if battery operated and communication mechanism from sensor to digital processing engine.
Cosmic Circuits engineers work with customers through this phase to define an optimal solution after weighing feasibility of IC implementation.
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Arasan Total IP Solutions
Arasan Chip Systems’ mobile connectivity products provide system architects and SoC design teams with silicon-proven, validated IP that helps ensure the integration and verification of digital, analog and software components in the shortest possible time with the lowest risk. These IP solutions have been incorporated into millions of mobile devices, including smartphones, tablets, digital cameras, portable game consoles, and many others.
Arasan’s high-quality Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers traffic generators, software stacks and drivers, and optional customization services for MIPI, USB, SD, SDIO, MMC/ eMMC, CF, UFS and many other popular standards.
Prakash Kamath, VP of Engineering for Arasan Chip Systems explains Total IP Solutions in this video:
As the last quarter unfolded, it became clear that the semiconductor market continues to lag amid the global economic and political concerns around the world. The events continue to unfold and despite progress on various fronts, lingering concerns still inject caution into the overall outlook. To navigate this turbulence, Open-Silicon has maintained a focused on its core beliefs: customer-centric solutions, operational excellence and customer satisfaction. With those in mind let’s review recent developments at the company.
First of all, throughout 2011 our customers increasingly asked us for ARM®-based solutions, in both mobile and non-traditional ARM markets. In response, this summer we greatly expanded our relationship with ARM, becoming one of a few companies worldwide offering ARM-based ASIC design services backed with a comprehensive multi-year ARM licensing agreement. And we did not stop there – to further integrate ARM processors, graphics and system IP into a complete solutions package, we created the ARM Center of Excellence. Open-Silicon’s ARM Center of Excellence builds upon our foundation of ASIC design and manufacturing by adding SoC architecture and transaction-level modeling, system prototyping, ARM-based software, and board design services to complete the solutions offering.
Another recent trend has been growing demand for our Interlaken Controller IP, which is helping core networking infrastructure devices achieve the next level of performance. However, increased performance has highlighted the challenge in another area: memory bandwidth. Our customers increasingly also need solutions to address memory interface bandwidth, especially in packet-processing and high-performance computing systems. In response, this October Open-Silicon joined DRAM leaders Micron and Samsung in the new Hybrid Memory Cube (HMC) Consortium. As a founder and developer member of the Consortium, Open-Silicon will help ASIC and ASSP developers access the revolutionary HMC technology through a combination of industry standards development, HMC interface IP, and HMC-specific design services.
HMC, leveraging Through-Silicon Via (TSV) technology and state-of-the-art DRAM design, promises to bring unparalleled bandwidth (over 15X better than DDR3), footprint savings (90% less space), and major power savings compared to DDR-based solutions. I believe HMC will enable new solutions in networking, cloud computing and high-bandwidth applications, which are currently not possible due to constraints in processor-memory interfaces.
In the coming quarter, Open-Silicon plans to expand its team and add capabilities to go deeper into system-level solutions and hardware-software design. In addition to our conventional capabilities with ASICs, we strongly believe that with our focus on system-level solutions, ARM-based SoCs and differentiated memory solutions, we will continue bringing significant value to our customers.
When it comes to selecting IP, the biggest concerns of design engineers are interoperability (will IP from one vendor work with IP from another), ease of integration, and the quality and reliability of the resulting system.
So who should you turn to for your MIPI IP? The answer is Arasan (www.arasan.com), which provides a total MIPI IP solution. We are deep domain experts who have been with the MIPI Alliance since its inception and who were the first to demonstrate working MIPI solutions. All of the MIPI board members are our customers, as are many of the 200+ contributing members.
Figure 3. Arasan offers a total MIPI IP solution.
As a simple example, consider the CSI-2 and DSI interfaces shown in Figure 1. Some IP vendors supply the CSI-2 transmitter, some supply the CSI-2 receiver and a few supply both; similarly for the DSI device and host controllers. But no single IP vendor has all of these cores… except for Arasan.
Actually, the real-world situation is even more complex, because some IP vendors supply only the digital portions of the IP, leaving their customers to source the D-PHY IP from another vendor. In fact, some IP vendors supply only the D-PHY and/or M-PHY, but have no deep understanding with regard to the digital portions of the interfaces. The problem is that, as was noted in the discussions associated with Figure 1, the digital IP blocks communicate with the D-PHY using the PPI (PHY Protocol Interface), but this interface is only optional and is subject to interpretation; suffice it to say that the end result may not be pretty.
Arasan can supply both the digital IP and the analog PHY for any existing MIPI standard, including CSI-2, DSI, SLIMbus, and HSI, along with the D-PHY and M-PHY. But there’s more to IP than RTL (for the digital portions) and GSDII (for the analog blocks). When we say that Arasan provides a total MIPI IP solution, we mean that we supply RTL (GDSII where applicable), ESL (Behavioral) and Transaction-Level Models (TLMs), Verification IP (VIP), software drivers and stacks, reference designs, and full hardware development kits (HDKs) and platforms.
And, as domain experts, in addition to the MIPI IP itself, we also offer consultation services with regard to alternative architectural scenarios such as the optimum number of lanes to use for a particular application. Furthermore, we provide unparalleled support direct from the engineers who develop our IP, which means you simply cannot ask our engineers something about the IP that they don’t know.
Another consideration is the quality of the verification IP (VIP) that accompanies the main IP cores. IP vendors typically create both the IP cores and the corresponding VIP. One potential problem is that the interface specifications aren’t always 100% comprehensive. The result is that it’s possible to introduce a non-standard interpretation of a corner case condition (possibly even a full-up error) into the IP and to then create VIP that tests for the incorrect implementation.In order to address this issue, although we create and ship our own VIP, we use VIP from other leading vendors to double-check our IP.
Summary
The MIPI suite of interfaces – coupled with the D-PHY and M-PHY physical layers – help designers of mobile and consumer products to reduce cost, complexity, power consumption, and EMI while increasing bandwidth and performance. MIPI addresses all of the subsystems found in mobile and consumer products, including graphics (cameras and displays), audio, radio, control, storage, and power management.
Arasan can supply a total MIPI IP solution for any existing MIPI standard, including digital IP, analog/PHY IP, verification IP (VIP), software stacks and drivers, hardware development kits, and… the list goes on. In addition to offering consultation services with regard to alternative architectural scenarios and customization, Arasan also provides unparalleled support direct from the engineers who develop our IP.
We are deep domain experts who have been with the MIPI Alliance since its inception and who were the first to demonstrate working MIPI solutions. All of the MIPI board members are our customers, as are many of the 200+ contributing members. The quality of our total MIPI IP solution, coupled with the fact that Arasan can supply a total MIPI IP solution for any existing MIPI standard, explains why Arasan is the MIPI IP vendor of choice. Call Arasan today and let us MIPIfy you!
Please visit www.mipi.org for further information on MIPI in general.
Please visit www.arasan.com for further information on Arasan’s total MIPI IP solutions.
** End of Article **
Prakash Kamath is the Vice President of Engineering at Arasan Chip Systems (www.arasan.com). Responsible for almost 200 engineers worldwide, Prakash has 29 years of extensive Design and Management experience. Prakash has successfully contributed to establishing Arasan’s “Total IP Solution” and has been instrumental in achieving Arasan’s leadership position with regard to Solid-State Storage and MIPI IP solutions. Prior to joining Arasan in 2002, Prakash has held several design and management positions in companies like AMD, National, and Chips & Technologies. Prakash holds a BS degree from the University of Madras, India, and an MS degree from the University of California, Santa Barbara, USA.
** End of Part 2 **
Prakash Kamath is the Vice President of Engineering at Arasan Chip Systems (www.arasan.com). Responsible for almost 200 engineers worldwide, Prakash has 29 years of extensive Design and Management experience. Prakash has successfully contributed to establishing Arasan’s “Total IP Solution” and has been instrumental in achieving Arasan’s leadership position with regard to Solid-State Storage and MIPI IP solutions. Prior to joining Arasan in 2002, Prakash has held several design and management positions in companies like AMD, National, and Chips & Technologies. Prakash holds a BS degree from the University of Madras, India, and an MS degree from the University of California, Santa Barbara, USA.
There are so many aspects to MIPI that it can be difficult for newcomers to take everything in, so let’s start with the Camera Serial Interface (CSI) and the Display Serial Interface (DSI). Currently in deployment, CSI-2 and DSI each require a maximum of six signals depending on the number of lanes used by the designer. Also, as illustrated in Figure 1, CSI-2 and DSI both share a common PHY (physical interface) known as the D-PHY, which is designed so as to offer high-speed with low power consumption and low EMI.
Figure 1. A high-level view of a product utilizing CSI-2 and DSI.
In particular, observe the way in which the PHY Protocol Interface (PPI) is used to communicate between the D-PHY and the higher-level protocols. We will return this interface later in this article when we come to discuss the various things design teams have to consider when selecting MIPI IP from different IP vendors.
It’s important to note that different systems may perform processing tasks in different ways. Consider the camera sensor, for example. Some sensors deliver their captured data raw directly to the application processor/SoC, leaving it to perform any required post-processing. Other camera sensors may pre-process the captured data and then hand the result over to the application processor/SoC. The CSI-2 interface can handle all such use cases.
Also of interest is the fact that even though they transport data in a serialized form, both CSI-2 and DSI maintain any real-time information associated with the data stream; for example the DSI will include event data such as V-Sync and H-Sync information.
Two other MIPI standards that are currently in deployment and that deserve mention are SLIMbus (Serial Low-power Inter-chip Media Bus) and HSI (High-speed Synchronous Serial Interface). SLIMbus is a low-power, low-speed peripheral bus that supports multiple clock/sample rates and is used to handle things like control signals and audio channels. SLIMbus can be used to replace existing I2C and I2S interfaces while offering more features and requiring the same or less power than the two combined. Meanwhile, HSI is a general-purpose interface that offers intermediate bandwidth capabilities between SLIMbus and the CSI-2 and DSI interfaces.
Emerging M-PHY-based MIPI Protocols
As discussed above, the original MIPI physical layer was the D-PHY, but the industry is starting to transition to a next-generation physical layer called the M-PHY. Both of these PHYs offer either high-speed or low-power signaling. The M-PHY uses fewer pins, but offers more options and flexibility and faster signaling, scaling up to 6 GB/sec. In the same way that CSI-2 and DSI conceptually “ride on top” of the D-PHY, a variety of high-level protocols share the M-PHY as illustrated in Figure 2.
Figure 2. A high-level view of emerging M-PHY-based protocols.
The Unified Protocol (UniPro) specification defines a layered protocol for interconnecting devices and components within mobile and consumer electronic systems. It is applicable to a wide range of component types including application processors, co-processors, and modems, as well as different types of data traffic including control messages, bulk data transfer, and packetized streaming.
The UFS (Universal Flash Storage) interface provides a simple standard interface aimed at the non-volatile memories (NVMs) that are used in mobile and consumer devices.UFS is a JEDEC standard that uses MIPI standards as a subset for the lower level protocols.
The CSI-3 and DSI-2 protocols are the next-generation versions of the currently deployed CSI-2 and DSI protocols, respectively. These new versions support the higher bandwidths and resolutions that will be required by emerging products, including 3D cameras and displays.
Also of interest is the LLI (Low Latency Interface), which provides low latency chip-to-chip communications. Meanwhile, the low-power, high-speed DigRFv4 interface can be used to link the application processor/SoC to the baseband IC and the baseband IC to the RF IC. Furthermore, the SSIC (SuperSpeedInterChip) specification, which is being developed in collaboration between the USB 3.0 group and the MIPI Alliance, will provide USB 3.0 speeds with fewer pins and less power, and will also allow reuse of existing USB drivers (this interface is currently under definition).
MIPI is Poised for Exponential Growth
Although the MIPI Alliance was formed eight years ago at the time of this writing, defining standards of this level of sophistication requires substantial amounts of time and effort. Thus, the works of the MIPI Alliance have only recently begun to come to fruition. However, in the same way that a snowball rolling downhill gathers size and momentum, the “MIPI snowball” has now started to roll!
According to IP Nest (www.ip-nest.com), MIPI is expected to reach 100% penetration in smartphones by 2013. And MIPI is no longer of interest only in the mobile market. MIPI has the potential to become the standard across the whole consumer product domain – anywhere where there’s a processor and a bunch of peripheral devices. In fact, according to InStat (www.instat.com), MIPI will have achieved 70% penetration in all forms of electronic consumer and computing devices by 2016.
Prakash Kamath is the Vice President of Engineering at Arasan Chip Systems (www.arasan.com). Responsible for almost 200 engineers worldwide, Prakash has 29 years of extensive Design and Management experience. Prakash has successfully contributed to establishing Arasan’s “Total IP Solution” and has been instrumental in achieving Arasan’s leadership position with regard to Solid-State Storage and MIPI IP solutions. Prior to joining Arasan in 2002, Prakash has held several design and management positions in companies like AMD, National, and Chips & Technologies. Prakash holds a BS degree from the University of Madras, India, and an MS degree from the University of California, Santa Barbara, USA.
Everything is going mobile – smartphones, digital cameras and video recorders, tablet computers, media players, game consoles, and the list goes on… These products are required to perform numerous tasks, including handling a wide variety of sensors such as microphones,image sensors, magnetic compasses, 3-axis accelerometers, and sophisticated touch screens. They are also used to capture and play high-definition audio, capture and process images and videos, display high-definition video and graphics, and use Wi-Fi and/or 2G/3G/4G to provide full access to the Internet and to support GPS navigation and location-based services.
Of course every product is different, so for the purposes of these discussions let’s consider a “generic” battery-powered system containing – amongst other things – an application processor, some solid-state memory, sensors in the form of a digital camera and a microphone, output devices in the form of a display screen and a loudspeaker, a baseband IC, and an RF chip. In some cases, many of these functions – excluding peripheral components like the sensors and output devices – may be combined in a single System-on-Chip (SoC) device. Alternatively, one or more SoCs may be used to augment the capabilities of an off-the-shelf application processor. Ultimately, the product will need to employ some sort of chip-to-chip communication mechanism; also sensor-to-chip and chip-to-display communications.
When many people hear the term intellectual property (IP) in the context of silicon chips, their knee-jerk reaction is often to think of “cool” things like microprocessor (ARMTM, MIPSTM) and digital signal processor (DSP) cores. In addition to these cores, however, the design engineers working “in the trenches” know that some of the most important – and numerous – IP cores that they build into their SoCs are used to implement interface functions.
Over the course of time, a profusion of interface standards evolved, such as the UART protocol, I2C, I2S, SPI, SDIO, and so forth. Also, a variety of parallel interface standards associated with camera sensors and display devices appeared on the scene. The result is a morass of confusion. For example, designers of a mobile device may have to handle as many as five competing and proprietary physical-layer (PHY) interfaces for any given system function.
Having multiple standards negatively affects interoperability, thereby limiting the options available to the product developer. It would typically not be possible to replace an existing sensor with a different, more attractively priced component, for example, because the two devices will almost invariably be based on different interface standards.
In the case of parallel interfaces, which typically involve more than 10 signals in the case of camera sensors and 20 or more signals in the case of displays, supporting multiple busses can lead to routing congestion. There’s also the expense, size, and weight involved with parallel connectors. And another consideration is reliability, because each signal and solder joint is a potential cause of failure.
And yet one more factor to consider is that as the silicon chips used in mobile devices are implemented in new technology nodes, the sizes of the silicon dice shrink, which means they can be encapsulated in smaller, lighter packages. However, these packages will support fewer input/output (I/O) pins, which makes parallel interfaces even less attractive.
In 2003, in order to address all of these issues for mobile devices, a consortium of companies formed the MIPI Alliance. The goal of MIPI (www.mipi.org) is to define a suite of interfaces for use in mobile and consumer products, where these interfaces reduce cost, complexity, power consumption, and EMI while increasing bandwidth and performance. MIPI addresses the following system elements:
It’s important to note that MIPI does not imply a single interface or protocol. Instead, MIPI embraces a suite of protocols and standards that address the unique requirements of the various subsystems. Furthermore, as opposed to the multiple physical layers associated with conventional interfaces, MIPI interfaces, when required, are layered on top of only two physical layers: the D-PHY or the M-PHY. The following discussions introduce the main MIPI elements that are already in deployment or are soon to be deployed. Also discussed are some considerations with regard to selecting MIPI IP.
Prakash Kamath is the Vice President of Engineering at Arasan Chip Systems (www.arasan.com). Responsible for almost 200 engineers worldwide, Prakash has 29 years of extensive Design and Management experience. Prakash has successfully contributed to establishing Arasan’s “Total IP Solution” and has been instrumental in achieving Arasan’s leadership position with regard to Solid-State Storage and MIPI IP solutions. Prior to joining Arasan in 2002, Prakash has held several design and management positions in companies like AMD, National, and Chips & Technologies. Prakash holds a BS degree from the University of Madras, India, and an MS degree from the University of California, Santa Barbara, USA.
The TVS OVM SDCARD Slave VIP is a highly flexible and configurable verification IP which can be easily integrated in any OVM SOC environment. The TVS OVM SD Card Slave VIP supports SDSC, SDHC with Non-UHS and UHS mode, SDXC and also supports 1, 4 and 8 bit data width. Associative Array’s have been used as memory to improve simulation speed and provide a scalable solution. The VIP comes with an Emulatable RTL interface and a Bus Monitor which performs Setup, Hold and clock width checks on every cycle for all configurations. The monitor also performs protocol checks and reports errors for non compliance with SDCARD 2.0 Specification. The VIP has been used to verify an SDCard interface for a chip that has fully first-time working silicon.
Using external VIP (Verification IP) brings several advantages including:
Availability
Independence in both checkers and coverage
Robustness from use in several environments
However, the VIP must be developed in such a way that it is easy for the user to incorporate the VIP into their environment. That is the reason OVM has been chosen for ease of integration into complex SOC Verification environments which are used by both SW and HW teams to verify their designs.
1.2 Feature Set
OVM SD Card slave VIP is complaint to SDCARD 2.0 specification.
Lower versions supported on configuration.
Supports huge memory efficiently.
Supports 1/4/8 bit data bus.
Supports SDSC, SDHC with Non-UHS and UHS mode and SDXC.
Performs protocol checks against SDCARD 2.0
Supports write protect.
Randomized error responses.
Backdoor write and read API’s provided.
Configurable busy delay
Configurable response timeout
Random CRC insertion on configuration to test error scenarios
Delay between read command and start bit of data block is configurable.
Similar configuration is available for write command
Configurable card programming error.
SDHC and SDXC are Silicon Proven VIPs
1.3 Block Diagram and Description
SDCARD Device VIP from TVS is compliant with OVM 2.1 Methodology and also compliant to SDCARD 2.0. It uses all the latest OVM constructs and also is very flexible for integration into various complex SOC Verification environments. It consists of the following components
Driver
Sequencer
Receiver
Engine
Register Factory and Config Space
Emulatable RTL Interface
SDCARD Memory is modelled into a flexible Associative Array and can be accessed through various API’s provided to the USER where data can be read and written into the memory.
1.4 Benefits of OVM and Industry Trends
Open
Written in IEEE 1800 SystemVerilog
Runs on any simulator supporting the IEEE 1800 standard
Verified on Cadence’s Incisive and Mentor Graphics’ Questa Verification Platform
True open-source license agreement (Apache 2.0)
Interoperable
Ensures VIP interoperability across ecosystem & simulators
Enables VIP ‘plug and play’ functionality for designers
Ensures interoperability with other high level languages
1.5 About TVS
TVS delivers an independent verification service that not only reduces your costs and time-to-market, but also improves product quality.
TVS combines skills and experience in software testing, hardware verification and outsourcing to provide customers with an efficient, well-managed, quality assurance service.
TVS provides both consultancy and execution services using experienced engineering resources in several locations around the world. TVS removes the pain and risk from outsourcing leaving you with just the benefits.
