Graham is Sr. Director of Marketing at Real Intent. He has over 20 years experience in the design automation industry. Occasionally he writes blogs for the Dominion of Design. The views and opinions expressed in this blog are his alone and not those of his employer.
Mystified About MIPI? Let Us MIPIfy You! – Part 2
November 9th, 2011 by Graham Bell
CSI-2, DSI, and the D-PHY
There are so many aspects to MIPI that it can be difficult for newcomers to take everything in, so let’s start with the Camera Serial Interface (CSI) and the Display Serial Interface (DSI). Currently in deployment, CSI-2 and DSI each require a maximum of six signals depending on the number of lanes used by the designer. Also, as illustrated in Figure 1, CSI-2 and DSI both share a common PHY (physical interface) known as the D-PHY, which is designed so as to offer high-speed with low power consumption and low EMI.
Figure 1. A high-level view of a product utilizing CSI-2 and DSI.
In particular, observe the way in which the PHY Protocol Interface (PPI) is used to communicate between the D-PHY and the higher-level protocols. We will return this interface later in this article when we come to discuss the various things design teams have to consider when selecting MIPI IP from different IP vendors.
It’s important to note that different systems may perform processing tasks in different ways. Consider the camera sensor, for example. Some sensors deliver their captured data raw directly to the application processor/SoC, leaving it to perform any required post-processing. Other camera sensors may pre-process the captured data and then hand the result over to the application processor/SoC. The CSI-2 interface can handle all such use cases.
Also of interest is the fact that even though they transport data in a serialized form, both CSI-2 and DSI maintain any real-time information associated with the data stream; for example the DSI will include event data such as V-Sync and H-Sync information.
Two other MIPI standards that are currently in deployment and that deserve mention are SLIMbus (Serial Low-power Inter-chip Media Bus) and HSI (High-speed Synchronous Serial Interface). SLIMbus is a low-power, low-speed peripheral bus that supports multiple clock/sample rates and is used to handle things like control signals and audio channels. SLIMbus can be used to replace existing I2C and I2S interfaces while offering more features and requiring the same or less power than the two combined. Meanwhile, HSI is a general-purpose interface that offers intermediate bandwidth capabilities between SLIMbus and the CSI-2 and DSI interfaces.
Emerging M-PHY-based MIPI Protocols
As discussed above, the original MIPI physical layer was the D-PHY, but the industry is starting to transition to a next-generation physical layer called the M-PHY. Both of these PHYs offer either high-speed or low-power signaling. The M-PHY uses fewer pins, but offers more options and flexibility and faster signaling, scaling up to 6 GB/sec. In the same way that CSI-2 and DSI conceptually “ride on top” of the D-PHY, a variety of high-level protocols share the M-PHY as illustrated in Figure 2.
Figure 2. A high-level view of emerging M-PHY-based protocols.
The Unified Protocol (UniPro) specification defines a layered protocol for interconnecting devices and components within mobile and consumer electronic systems. It is applicable to a wide range of component types including application processors, co-processors, and modems, as well as different types of data traffic including control messages, bulk data transfer, and packetized streaming.
The UFS (Universal Flash Storage) interface provides a simple standard interface aimed at the non-volatile memories (NVMs) that are used in mobile and consumer devices.UFS is a JEDEC standard that uses MIPI standards as a subset for the lower level protocols.
The CSI-3 and DSI-2 protocols are the next-generation versions of the currently deployed CSI-2 and DSI protocols, respectively. These new versions support the higher bandwidths and resolutions that will be required by emerging products, including 3D cameras and displays.
Also of interest is the LLI (Low Latency Interface), which provides low latency chip-to-chip communications. Meanwhile, the low-power, high-speed DigRFv4 interface can be used to link the application processor/SoC to the baseband IC and the baseband IC to the RF IC. Furthermore, the SSIC (SuperSpeedInterChip) specification, which is being developed in collaboration between the USB 3.0 group and the MIPI Alliance, will provide USB 3.0 speeds with fewer pins and less power, and will also allow reuse of existing USB drivers (this interface is currently under definition).
MIPI is Poised for Exponential Growth
Although the MIPI Alliance was formed eight years ago at the time of this writing, defining standards of this level of sophistication requires substantial amounts of time and effort. Thus, the works of the MIPI Alliance have only recently begun to come to fruition. However, in the same way that a snowball rolling downhill gathers size and momentum, the “MIPI snowball” has now started to roll!
According to IP Nest (www.ip-nest.com), MIPI is expected to reach 100% penetration in smartphones by 2013. And MIPI is no longer of interest only in the mobile market. MIPI has the potential to become the standard across the whole consumer product domain – anywhere where there’s a processor and a bunch of peripheral devices. In fact, according to InStat (www.instat.com), MIPI will have achieved 70% penetration in all forms of electronic consumer and computing devices by 2016.
** End of Part 2 **
Prakash Kamath is the Vice President of Engineering at Arasan Chip Systems (www.arasan.com). Responsible for almost 200 engineers worldwide, Prakash has 29 years of extensive Design and Management experience. Prakash has successfully contributed to establishing Arasan’s “Total IP Solution” and has been instrumental in achieving Arasan’s leadership position with regard to Solid-State Storage and MIPI IP solutions. Prior to joining Arasan in 2002, Prakash has held several design and management positions in companies like AMD, National, and Chips & Technologies. Prakash holds a BS degree from the University of Madras, India, and an MS degree from the University of California, Santa Barbara, USA.