Posts Tagged ‘mixed-signal’
Tuesday, January 26th, 2016
CC-100 PowerOp IP
The CC-100 PowerOp IP harvests waste energy (logic overlap current) in digital and mixed signal SOC’s, and recycles a portion of it back into the system for an overall lower system power profile. This IP allows users to save watts of power, depending on how much digital or dynamic power is being consumed in a given SOC, and can fit in the left-over “white space” of most SOC or processor designs.
In short, this IP turns the standard power saving techniques around, saving power when circuits turn on, thus complimenting, not competing with, standard industry techniques normally used to save power.
The CC-100 PowerOp IP has been realized in Proof-of-Concept silicon and has been produced and characterized on the IBM CM018RF RF manufacturing process.
The CC-100 PowerOp IP import is scalable to any IC process ranging from .6um to 28nm, available on request from CurrentRF Proof-of-concept, characterization, and design aid documents and boards for the CC-100 IP are also available on request.
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Tags: automotive electronics, concurrent design, Dynamic Power Dissipation, IC Verification, IP, IP reuse, mixed-signal, SoC integration
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Friday, October 30th, 2015
On November 11th and 12th, DVCon Europe will once again take place in the lovely city of Munich. The inaugural event last year demonstrated a clear need for this event in Europe, with a focus on practical information that allowed the attendees to get a rapid, all-encompassing update on a broad range of design and verification techniques. Furthermore, it also showed the international audience those areas where Europe leads, influencing EDA development and thinking on a global basis.
This year’s show promises an even bigger and better program. It is expected to grow significantly, and indeed, early registrations, the size of the exhibit, and the number of papers and tutorials all bear this out. The theme of the conference, focused on the predominantly European automotive semiconductor segment, acts as a driver for next-generation design and verification across the entire industry, given the absolute reliability requirements of these devices. Subject areas, including system-level abstraction, analog/mixed-signal devices, UVM and other advanced verification, will all be discussed during a number of networking opportunities including a Gala dinner, included as part of the registration.
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Tags: analog, communication, Dave Kelf, DVCon, eda, Euro, Europe, FPGA, mixed-signal, SystemC, UVM
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Wednesday, August 20th, 2014
Mixed-signal silicon design, bringing the worlds of analog and digital technology onto a single die, has never been an easy task. Formerly, the analog and digital teams would work independently on their designs, leaving the place and route team with the thankless task of integrating everything onto a single chip. A microcontroller design, with all of its carefully thought out peripherals, would be routed leaving analog-sized holes for the oscillator, ADC and transceivers needed to complete the design.
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Tags: ADSP-CM40X, Analog-Digital, ARM, mixed-signal, On-Chip Integration, Richard York, silicon devices, XMC4000
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