By David Abercrombie and Michael White
No matter what process node you’re working at, or how big or how complex your integrated circuit (IC) design is, design enablement is a complex process that goes through multiple stages. The faster you get your design to market, the better your chances of achieving your market goals. But getting your design to the foundry on schedule, while ensuring the final product will not only be manufacturable, but also provide the intended performance and reliability, all depends on achieving and maintaining high productivity and quality of results throughout the design flow.
IC design companies, like any other business, constantly look for ways to improve and speed up their processes. One approach that has recently gained significant traction is the idea of “shifting left”—performing design layout verification and optimization earlier in the design flow, instead of waiting until the signoff verification stage. However, simply shifting signoff physical verification to earlier stages of the design flow is neither practical nor productive. Signoff verification is intended to apply to full chip designs where all components are complete and connected. Running signoff verification on incomplete or “dirty” designs is not only time-consuming, but also returns millions of errors, many of which are irrelevant, as they are caused by the incomplete nature of the layout. Hardly the increase in productivity the design companies were hoping for.
