EDACafe Industry prediction – Agnisys

By Anupam Bakshi, CEO, Agnisys

Anupam Bakshi

The trends that I talked about in my 2020 Predictions  will continue with even more vigor.

Automatic generation of the RTL design will continue beyond the hardware-software interface (HSI) layer. It will encompass a whole custom IP, enabling users to generate much of their design directly from their specifications. The generation process will include high-quality documentation suitable for inclusion in user manuals.

The range of available standard IP will continue to grow, with many configuration and customization options. Automated integration of both standard and custom IP to build subsystems and a complete SoC will expand to include all aspects of SoC creation. The generated RTL designs will include custom and standard bus interfaces, functional safety mechanisms to detect and correct errors, and clock domain crossing (CDC) logic.

Automatic verification will continue to include not only testbench generation but test generation as well, plus generation of assertions for use in both simulation and formal verification. Generated C/C++ code will be used by programmers to develop and test their embedded code and device drivers.

Finally, the RISC-V movement will continue moving along briskly with greater need of automated solutions for IP and system level modeling.

Category: EDA Predictions

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