Guest Blogger 
Michael Hopkins, founder of CurrentRF
Michael Hopkins is the founder of CurrentRF, A California based company founded in 2002. Through activities with CurrentRF, Michael developed the RFDAC methodology and Current Reuse Mixer (the CRF2101) in 2002, and more recently, the PowerOptimizer (PowerOp) methodologies and technologies the … More » IP Cuts Dynamic Power Dissipation 20% More Than Can Be Achieved With Standard TechniquesJanuary 26th, 2016 by Michael Hopkins, founder of CurrentRF
CC-100 PowerOp IP The CC-100 PowerOp IP harvests waste energy (logic overlap current) in digital and mixed signal SOC’s, and recycles a portion of it back into the system for an overall lower system power profile. This IP allows users to save watts of power, depending on how much digital or dynamic power is being consumed in a given SOC, and can fit in the left-over “white space” of most SOC or processor designs. In short, this IP turns the standard power saving techniques around, saving power when circuits turn on, thus complimenting, not competing with, standard industry techniques normally used to save power. The CC-100 PowerOp IP has been realized in Proof-of-Concept silicon and has been produced and characterized on the IBM CM018RF RF manufacturing process. The CC-100 PowerOp IP import is scalable to any IC process ranging from .6um to 28nm, available on request from CurrentRF Proof-of-concept, characterization, and design aid documents and boards for the CC-100 IP are also available on request.
Available CC-100 IP support documents include the CC_100_IP_Proof_of_Concept_and Characterization.pdf, which shows the Proof-of-Concept Silicon performance with an onboard BIST engine of ten logic gates providing the on-chip stimulus generator for the IP. The CC_100_IP_Structure and Design Aid.pdf shows the unique way that this IP fits into mixed signal and digital designs, what it can do to lower power dissipation in host designs, and also shows the predictive capability and procedures needed for successful IP integration into mixed signal and digital chips. For additional info or documentation, contact us at the following: Michael.Hopkins@CurrentRF.com http://www.CurrentRF.com Tags: automotive electronics, concurrent design, Dynamic Power Dissipation, IC Verification, IP, IP reuse, mixed-signal, SoC integration Category: DesignCon |
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