Enough can’t be said about the power to educate based on experience. At this year’s DAC, a few of Jasper’s top users volunteered to give seminars on their best practices for using Jasper Formal technology. If you happened to miss DAC or did attend but didn’t get a chance to visit the Jasper booth, here’s your chance to view the on-line videos from ST, ARM, and NVIDIA on how they utilized Jasper Formal technology to get ahead in their designs.
ST: Low Power Verification and Optimization with Jasper Formal
ST Microelectronics talked about the verification challenges associated with sophisticated low-power designs, and ways those challenges are being addressed by Jasper’s power-aware formal verification technology. The seminar detailed how Jasper’s low-power verification solution applies to:
- Parsing CPF information to enable power-aware formal analysis
- X-propagation due to shutting down power
- Functional impact due to power-down
- Power-up state analysis
- Exploration of power-state
