Artificial Intelligence updates – in terms of new IP and new startup funding – make up a significant part of this week’s news roundup, while other recurring themes include optics/photonics applications and IoT security.

AI updates: Cadence, Deep Vision, Axelera

Cadence has unveiled its Tensilica AI Platform for AI SoC development, including three product families for the low, mid and high end. Built upon the Tensilica DSPs, the Tensilica AI Platform adds a new companion AI neural network engine (NNE) and neural network accelerators (NNAs). The “AI Base” family includes the Tensilica HiFi DSPs and ConnX DSPs, combined with AI instruction-set architecture extensions. The “AI Boost” family adds a companion NNE, initially the Tensilica NNE 110 AI engine, which scales from 64 to 256 GOPS. The “AI Max” family encompasses the Tensilica NNA 1xx AI accelerator family—currently including the Tensilica NNA 110 accelerator and the NNA 120, NNA 140 and NNA 180 multi-core accelerator options—which integrates the AI Base and AI Boost technology. The multi-core NNA accelerators can scale up to 32 TOPS, while future NNA products are targeted to scale to 100s of TOPS. Targeting intelligent sensor, IoT, audio, mobile vision/voice AI and ADAS applications, the Tensilica AI Platform features a common software platform and – according to Cadence – delivers optimal power, performance and area.

Deep Vision has received $35 million in a Series B financing round led by Tiger Global. Deep Vision’s AI processor, named ARA-1, targets camera-based applications such as smart retail, driver-monitoring systems, smart city, drones, and factory automation. The company’s processor also provides natural language processing capabilities.

Read the rest of AI startups; microLED-based interconnect; silicon nitride photonics; cloud-native automotive software; new solid-state LiDAR

No shortage of interesting news this week – both from the industry and from academia – still it’s worth devoting some space to a Tesla event that took place last month, showing how system-level assembly technologies can make a difference for supercomputers.

Fab and foundry updates: Intel, SMIC, X-Fab, Samsung

Intel’s CEO Pat Gelsinger has reportedly said the company will invest up to €80 billion over the next decade to build new chip fabs in Europe.

According to the Wall Street Journal, SMIC is teaming up with the Shanghai government to build an $8.87 billion chip production line in the city.

Germany-headquartered X-Fab Silicon Foundries is now able to support volume heterogeneous integration via Micro-Transfer Printing (MTP), thanks to a licensing agreement with X-Celeprint. Technologies that may be combined include SOI, GaN, GaAs and InP, as well as MEMS. X-Celeprint’s pick-and-place MTP technology stacks and fans-out ultra-thin dies.

Samsung Electronics has reportedly chosen the city of Taylor, Texas, as the site for its planned $17 billion new chip plant – which will be four times larger than Samsung’s existing fab in Austin. To attract the investment, the city of Taylor has reportedly offered Samsung a $314 million worth of tax breaks for the next ten years.

Source: official City of Taylor website

Read the rest of New fabs; Tesla training system; GaN CMOS; CUDA on Risc-V; Y Combinator startups

News about Arm-based and Risc-V-based processors make up most of the updates this week. As for Risc-V, besides the two startups mentioned below, new adopters include Imagination, which this year is re-entering the CPU market with designs based around the open ISA. Speaking of Arm, according to British newspaper “The Telegraph”, Tesla’s CEO Elon Musk has expressed his opposition to the Nvidia-Arm deal. The Sunday Telegraph also understands that Amazon and Samsung have lodged opposition to the deal with US authorities. As far as EDA is concerned, a very recent update is the resignation of Babak Taheri as chief executive officer of Silvaco and member of the board after two years in the role. The official press release does not provide any explanations for this decision. Let’s now move to the other news.

Translating C++ algorithms to RTL for Microchip FPGA programming

Microchip has added an HLS design workflow. called SmartHLS, to its PolarFire FPGA families that allows C++ algorithms to be directly translated to FPGA-optimized RTL code. The solution is aimed at applications involving edge compute, computer vision and industrial control algorithms that are developed natively in C++ by developers with little or no knowledge of underlying FPGA hardware. The SmartHLS design suite is based on the open-source Eclipse integrated development environment. According to Microchip, the SmartHLS tool requires up to ten times fewer lines of code than an equivalent RTL design.

Google reportedly developing Arm-based CPUs for notebook and tablet PCs

According to Nikkei Asia, Google is developing its own Arm-based CPUs for its notebook and tablet computers which run on the company’s Chrome operating system. Roll out would be planned for 2023. Google is also reportedly ramping up its efforts to build Arm-based mobile processors for its Pixel smartphones and other devices. The company is hiring chip engineers in the US and around the world, including in Israel, India and Taiwan.

Read the rest of Google reportedly developing Arm-based PC CPUs; new Risc-V-based datacenter processors; acquisitions

Catching up on some of the news from the last four weeks or so, Intel stands out with its late-July and mid-August announcements which we will briefly recall below – along with several more news from various areas. But first, a quick update on the Nvidia-Arm deal: according to the UK Government’s Competition and Markets Authority (CMA), this acquisition would “lead to a realistic prospect of a substantial lessening of competition”. Another quick update about GlobalFoundries, which – according to Reuters – has filed confidentially with U.S regulators for an initial public offering (IPO) in New York.

EDA updates: Cadence, Motivo, Avishtech

Anirudh Devgan to become Cadence CEO. Current Cadence CEO Lip-Bu Tan will transition to the role of executive chairman on December 15, 2021, with President Anirudh Devgan assuming the role of president and CEO at that time. Devgan has also joined the Cadence Board of Directors.

AI-enabled EDA tools developer Motivo raises $12 million financing. The Series A financing round is led by Intel Capital and follows earlier seed rounds of $8 million. Motivo’s technologies accelerate chip design utilizing a “learning-on-graph” methodology for automated data-driven feature extraction. According to the company, Motivo’s M-Graph and other explainable AI technologies can be applied across the entire design flow, from RTL code to layout geometries. With this approach, Motivo aims to compress the design-to-manufacturing process from years to months.

Read the rest of Intel process and architecture updates; AI in EDA attracting investors; Foxconn to add SiC and MEMS offering

Quarterly result announcements – either from Q1 or Q2 – make up a significant part of this week’s news roundup. Manufacturing capacity expansion continues to be a hot topic, but there is no shortage of other updates. Quantum computing research is also in the news with two announcements.

Record EDA and IP revenues in Q1 2021

According to the latest report from the ESD Alliance, in Q1 2021 the Electronic System Design industry revenue increased 17% to $3,157.17 million, marking the strongest first-quarter growth ever. The four-quarter moving average, which compares the most recent four quarters to the prior four, rose 15%, the highest annual growth since 2011. All product categories significantly contributed, with double-digit growth in the CAE, IC physical design/verification, PCB/MCM, and semiconductor IP segments. Geographically, the Americas, EMEA and APAC regions also reported double-digit growth. Outstanding figures have been achieved by IC physical design and verification revenue, which surged 34.4% to $682.5 million compared to Q1 2020; and by the Asia Pacific revenue, which increased 26.9% to $1,166.3 million compared to Q1 2020. Quoted by Semiconductor Engineering, Wally Rhines – executive sponsor of SEMI‘s Electronic Design Market Data Report – underlined the Chinese figures: “Year on year, the revenue in China was up 73%. And if you look at EDA only, separate from IP, it was up 99%,” he reportedly said.

EDA updates: Ansys cloud support, Julia Computing funding

In collaboration with Arm, Ansys is enabling simulation solutions for AWS Graviton2 processors, a more affordable way to access Amazon Web Services cloud computing resources. The initiative marks the first availability of Ansys’ semiconductor simulation solutions on the Arm Neoverse architecture. Beginning with the APL (Ansys Power Library) characterization tool, Ansys will offer more of its semiconductor analysis software product suite, supporting the Arm Neoverse architecture that is used by AWS Graviton2-powered Amazon Elastic Compute Cloud instances.

Read the rest of Record EDA-IP revenues; new fabs; Xilinx Vitis AI 1.4; quantum advancements

Investments – both announced and rumored – make up a significant part of this week’s news roundup. More updates concern automotive applications and AI chips.

Intel reportedly in talks to buy GlobalFoundries

According to the Wall Street Journal, Intel is exploring a deal to buy GlobalFoundries, in a move that would represent its largest acquisition ever. A deal could value GlobalFoundries at around $30 billion, sources said. It isn’t guaranteed that the acquisition will take place; alternatively, GloFo could proceed with a planned initial public offering. GlobalFoundries is owned by Mubadala Investment Co., an investment arm of the Abu Dhabi government. As noted by WSJ, AMD remains a big customer for GlobalFoundries, and that could complicate a takeover by Intel.

Rohm to invest in semiconductor startups

Japanese chipmaker Rohm has reportedly launched a 5 billion yen ($45.3 million) venture capital fund to invest in next-generation semiconductor technology. Among first beneficiaries is US startup Locix, a developer of cloud-based spatial intelligence solutions for commercial buildings, consumer homes and connected devices. Locix solutions capture location, visual and sensor data and combine them with data analytics to provide spatial awareness.  Based in San Bruno, CA, Locix is backed by several other Japanese investors, too.

Read the rest of Intel-GloFo rumors; semiconductor investments; in-vehicle data transmission; AI updates

Not surprisingly, several news this week are somewhat related to fabs and foundries – in terms of customer contracts, new fabs, acquisitions, equipment – as companies around the world are repositioning to take advantage of the semiconductor boom. Another interesting update concerns Simon Segars speaking about the Nvidia deal. More news is coming from the International Supercomputing Conference and from the latest MLPerf results.

Apple and Intel reportedly first to adopt TSMC’s 3 nm process

According to Nikkei Asia, Apple and Intel have emerged as the first adopters of TSMC’s 3-nanometer process ahead of its deployment as early as next year. Commercial output of such chips is expected to start in the second half of next year. Apple’s iPad will likely be the first devices powered by processors made using 3-nanometer technology. Intel is reportedly working with TSMC on at least two 3-nanometer projects concerning CPUs for notebooks and data center servers. Mass production of these chips is expected to begin by the end of 2022 at the earliest. Reportedly, the chip volume planned for Intel is more than that for Apple’s iPad.

Read the rest of Fab-related updates; Arm-Nvidia deal; HPC and ML rankings

Not just lithography: scaling to 2-nanometers and beyond involves many difficult manufacturing challenges. A virtual event and a series of blog posts from Applied Materials help understand how these problems can be solved with coordinated solutions based on new transistor architectures, new materials, new manufacturing processes

Over the past few years, the transition to EUV lithography has received a lot of attention as a key enabling technology for further IC scaling. But moving to the next advanced process nodes is not just about projecting smaller patterns; in fact, the resulting size reduction of every circuit feature opens a set of new, complex problems that need to be addressed in order to achieve the expected PPA benefits. Let’s take a look at these challenges with the help of Applied Material’s experts. In a ‘Logic Master Class’ held as a virtual event last June 16^th – still available on demand – and in a series of related blog posts, Mike Chudzik, Mehul Naik and Regina Freed addressed different aspects of the scaling of logic ICs, stressing the increasing importance of ‘design-technology co-optimization’ (DTCO). Applied Materials describes DTCO as a way to “reduce area-cost without changing the lithography and pitch,” using a combination of architectures, processes and materials. In this quick overview of the class, we will only summarize some of the general concepts.

Pitch scaling is not enough

The need for innovation stems from the fact that just building a smaller version of the same device – as in the traditional method, called pitch scaling or ‘intrinsic scaling’ – would lead to bad power and performance results and to increased device variability. This is because size reduction generates new limiting factors. Trying to generalize, one could say that there are mechanical limitations, electrical limitations, and process limitations. Mechanical limitations include the fact that some elements may become too weak to withstand mechanical stress; electrical limitations mostly refer to the increased resistance of current paths – signal or power – due to smaller cross section area; and process limitations include the fact that certain specific elements – e.g. certain material layers – cannot scale proportionally, or that patterning inaccuracy become a larger percentage of the intended feature. Collectively, these limitations are now determining the transition from FinFET to GAA (Gate-All-Around) transistors.

Read the rest of Scaling challenges and the increasing importance of design-technology co-optimization

According to industry association SEMI, semiconductor manufacturers around the world will start the construction of nineteen new high-volume fabs by the end of this year, and ten more fabs will be added in 2022. So it’s no surprise that several announcements this week concern new fabs. Besides rumors about a new European site, Intel is in the news also for its organizational changes that – to some extent – reflect the growing importance of AI and hyperscale data centers. Among other news is a further advancement of machine learning in EDA-related technologies, namely FPGA design tools; and a new manufacturing process enabling further scaling.

Intel reportedly in talks on a new fab near Munich, Germany

Intel is reportedly in talks with the German state of Bavaria to build a new fab, with the goal of countering the chip shortage that is damaging the automotive industry. According to the report, in recent months Intel has been seeking 8 billion euros (US$9.5 billion) in public subsidies to build a semiconductor manufacturing site in Europe. Reportedly, the Bavarian Economy Minister is strongly supporting the initiative. The Bavarian government has suggested a disused air base in Penzing-Landsberg, west of Munich, as a possible location for the factory. The German state of Bavaria is home to carmaker BMW, and the Munich area is a significant semiconductor manufacturing hub, hosting – among others – a large Texas Instruments factory.

Read the rest of New fabs; Intel reorganization; ML in FPGA design; thermal model standard; reducing via resistance